NDLI: Synthesis of transparent circuits for hierarchical and system-on-a-chip test

Content Provider	IEEE Xplore Digital Library
Author	Chakrabarty, K. Mukherjee, R. Exnicios, A.
Copyright Year	2001
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Duke Univ., Durham, NC, USA (Chakrabarty, K.)
Abstract	We propose a synthesis for test approach in which multiplexers are embedded in the behavioral models of the various modules constituting a hierarchical system. This approach can also be applied to system-on-a-chip designs in which synthesizable models are available for the embedded cores. The embedded multiplexers provide complete, single-cycle transparency, thereby offering a straightforward yet effective solution to the problems of test data propagation and test vector translation. In order to determine I/O bitwidths for single-cycle transparency, a global analysis is carried out using a graph-theoretic framework and an optimization method based on integer linear programming. Case studies using high-level synthesis benchmarks and an industrial-strength benchmark show that synthesis for transparency introduces very little area and performance overhead.
Sponsorship	Broadcom India
Starting Page	431
Ending Page	436
File Size	703155
Page Count	6
File Format	PDF
ISBN	0769508316
ISSN	10639667
DOI	10.1109/ICVD.2001.902696
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-01-07
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit synthesis Multiplexing Benchmark testing Circuit testing System testing Hierarchical systems System-on-a-chip Vectors Optimization methods Integer linear programming
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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