NDLI: Evaluation of the traffic-performance characteristics of system-on-chip communication architectures

Content Provider	IEEE Xplore Digital Library
Author	Lahiri, K. Raghunathan, A. Dey, S.
Copyright Year	2001
Description	Author affiliation: Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA (Lahiri, K.)
Abstract	The emergence of several communication architectures for system-on-chips provides designers with a variety of design alternatives. In addition, the need to customize the system architecture for a specific application or domain, makes it critical for a designer to be aware of (and to evaluate) the trade-offs involved in selecting an optimal system-level communication architecture. While it is generally known that different communication architectures may be better suited to serve the needs of different applications, very little work has been done on quantitatively comparing and characterizing their performance for different classes of on-chip communication traffic. In this paper, we present a detailed analysis of the performance of various system-on-chip communication architectures under different classes of on-chip communication traffic. We present high-level models of a few commonly used on-chip architectures, which take into account key architectural features, including their characteristic topologies and communication protocols. We present an efficient methodology to study the performance of each architecture, making use of (i) parameterized traffic generators, that help create a wide variety of on-chip communication traffic, and (ii) an implementation independent communication interface abstraction, to enable plug-and-play evaluation of alternative communication architectures. Our experiments show that the effectiveness of each architecture varies significantly, depending on the characteristics of the communication traffic (average communication rates of common architectures were seen to vary by as much as 409%). Additionally, they also demonstrate the criticality of judiciously selecting an on-chip communication architecture for a given application. We discuss the implications of our experiments, including the relative strengths and weaknesses of the considered architectures, the classes of traffic that each is well suited to, and requirements for system design tools and methodologies in order to support efficient communication architecture selection and customization.
Sponsorship	Broadcom India
Starting Page	29
Ending Page	35
File Size	953457
Page Count	7
File Format	PDF
ISBN	0769508316
ISSN	10639667
DOI	10.1109/ICVD.2001.902636
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-01-07
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	System-on-a-chip Computer architecture National electric code Traffic control Topology Computer applications Costs Power dissipation Design methodology Digital signal processing
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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