NDLI: On fault-simulation through embedded memories on large industrial designs

Content Provider	IEEE Xplore Digital Library
Author	Yadavalli, S. Kundu, S.
Copyright Year	2001
Description	Author affiliation: Intel Corp., Santa Clara, CA, USA (Yadavalli, S.)
Abstract	Modern microprocessor designs contain several embedded memory arrays that form register files, caches, TLBs, re-order buffers, etc. These arrays are an integral portion of the design and may sometimes drive substantial data-path and control logic blocks in a microprocessor. Fault-simulation and ATPG for state-of-the-art commercial microprocessor designs is complex and requires suitable engineering to make them successful. In this paper we discuss a framework for fault-simulation of large microprocessor designs containing hundreds of embedded memory arrays in use today. Embedded memory arrays come in a variety of flavours with different number of input and output ports and different access mechanisms. In this paper we discuss how these arrays can be described for the fault-simulator and present the data-structures and some of the algorithms for simulating faults through these arrays.
Sponsorship	Broadcom India
Starting Page	117
Ending Page	121
File Size	359247
Page Count	5
File Format	PDF
ISBN	0769508316
ISSN	10639667
DOI	10.1109/ICVD.2001.902649
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-01-07
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Automatic test pattern generation Logic testing Microprocessors Random access memory Registers Logic arrays Logic design Read only memory Workstations Educational institutions
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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