NDLI: FPGA hardware synthesis from MATLAB

Content Provider	IEEE Xplore Digital Library
Author	Haldar, M. Nayak, A. Shenoy, N. Choudhary, A. Banerjee, P.
Copyright Year	2001
Description	Author affiliation: MACH Design Syst. Inc., Schaumberg, IL, USA (Haldar, M.)
Abstract	Field Programmable Gate Arrays (FPGAs) have been recently used as an effective platform for implementing many image/signal processing applications. MATLAB is one of the most popular languages to model image/signal processing applications. We present the MATCH compiler that takes MATLAB as input and produces a hardware in RTL VHDL, which can be mapped to an FPGA using commercial CAD tools. This dramatically reduces the time to implement an application on an FPGA. We present results on some image and signal processing algorithms for which hardware was synthesized using our compiler for the Xilinx XC4028 FPGA with an external memory. We also present comparisons with manually designed hardware for the applications. Our results indicate that FPGA hardware can be generated automatically reducing the design time from days to minutes, with the tradeoff that the automatically generated hardware is 5 times slower than the manually designed hardware.
Sponsorship	Broadcom India
Starting Page	299
Ending Page	304
File Size	838412
Page Count	6
File Format	PDF
ISBN	0769508316
ISSN	10639667
DOI	10.1109/ICVD.2001.902676
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-01-07
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays MATLAB Signal synthesis Hardware design languages Array signal processing Java Libraries Optimizing compilers Mathematical model Design automation
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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