NDLI: Sub-Domino logic: ultra-low power dynamic sub-threshold digital logic

Content Provider	IEEE Xplore Digital Library
Author	Soeleman, H. Roy, K. Paul, B.
Copyright Year	2001
Description	Author affiliation: Purdue Univ., West Lafayette, IN, USA (Soeleman, H.)
Abstract	Sub-threshold static and ratioed logic have recently been proposed to satisfy the ultra-low power requirement in applications such as hearing aids, pace-makers, wearable wrist-watch computers etc. These logic circuits, however, can be operated only at lower frequencies due to lower supply voltage. To increase the frequency of operation, we propose sub-threshold dynamic logic: Sub-Domino logic. A standard full-adder circuit is implemented in both Sub-Domino and Sub-CMOS logic operating in the subthreshold region. Simulation results show that Sub-Domino logic has lower power consumption, smaller area (60% of Sub-CMOS logic), and is 3 times faster than Sub-CMOS logic. It is also shown that Sub-Domino logic has excellent noise margin.
Sponsorship	Broadcom India
Starting Page	211
Ending Page	214
File Size	397314
Page Count	4
File Format	PDF
ISBN	0769508316
ISSN	10639667
DOI	10.1109/ICVD.2001.902662
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-01-07
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic circuits Frequency Application software Hearing aids Wearable computers Voltage Computational modeling Circuit simulation Energy consumption Circuit noise
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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