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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Sinha, K. Sur-Kolay, S. Dasgupta, P.S. Bhattacharya, B.B. |
| Copyright Year | 2001 |
| Description | Author affiliation: Kalyani Eng. Coll., India (Sinha, K.) |
| Abstract | Topological routing has gained importance in state-of-the-art layout synthesis. This paper poses the problem of partitioning the routing area of a given placement into a minimum set of zones such that in each zone, no two pins belong to the same net. Thus, topological routing can be completed among the zones whereas within a zone the only wires are from a pin to the boundary of the zone. Hence, such partitioning may accelerate routing by reducing the problem size. The related problem of identifying a zone with maximum number of distinct pins is also considered here. Both problems are observed to be NP-hard. A genetic algorithm for the first one and a greedy heuristic for the second problem are proposed. Experimental results are observed to be near optimal in most of the cases. |
| Sponsorship | Broadcom India |
| Starting Page | 345 |
| Ending Page | 350 |
| File Size | 543899 |
| Page Count | 6 |
| File Format | |
| ISBN | 0769508316 |
| ISSN | 10639667 |
| DOI | 10.1109/ICVD.2001.902683 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2001-01-07 |
| Publisher Place | India |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Routing Pins Acceleration Educational institutions Engineering management Wires Genetic algorithms Integrated circuit interconnections |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electrical and Electronic Engineering Hardware and Architecture |
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