NDLI: Sequential circuits with combinational test generation complexity

Content Provider	IEEE Xplore Digital Library
Author	Balakrishnan, A. Chakradhar, S.T.
Copyright Year	1995
Description	Author affiliation: RUTCOR, Rutgers Univ., Piscataway, NJ, USA (Balakrishnan, A.)
Abstract	We propose a new design for testability (DFT) technique which, like full scan design, guarantees that tests can be derived using a combinational test generator. Our DFT technique has two important advantages over full scan design: (1) the area overhead incurred by our technique is significantly less and (2) the test application time for our technique is significantly lower. This DFT technique selects scan flip-flops and/or test points such that, in the test mode, the circuit will belong to a special class of sequential circuits that we call strongly balanced structures. We give a simple characterization for strongly balanced structures and provide efficient methods to select scan flip-flops and/or test points to reduce any sequential circuit to a strongly balanced structure. A complete test set can be obtained for a strongly balanced structure using a combinational test generator. Experimental results on ISCAS 89 benchmark circuits and production VLSI circuits show that both the DFT overhead and the test application time are substantially lower for our technique.
Starting Page	111
Ending Page	117
File Size	841701
Page Count	7
File Format	PDF
ISBN	0818672285
ISSN	10639667
DOI	10.1109/ICVD.1996.489468
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-01-03
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing Sequential circuits Sequential analysis Flip-flops Design for testability Benchmark testing Production Very large scale integration National electric code Shift registers
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A new definition and a new class of sequential circuits with combinational test generation complexity

Retiming algorithms with application to VLSI testability

Test time reduction in scan designed circuits

On using partial reset for pseudo-random testing

Partial scan design for technology mapped circuits

An extended class of sequential circuits with combinational test generation complexity

Optimum retiming of large sequential circuits

A new class of sequential circuits with combinational test generation complexity

Test configurations to enhance the testability of sequential circuits

Sequential circuits with combinational test generation complexity

Similar Documents

A new definition and a new class of sequential circuits with combinational test generation complexity

Retiming algorithms with application to VLSI testability

Test time reduction in scan designed circuits

On using partial reset for pseudo-random testing

Partial scan design for technology mapped circuits

An extended class of sequential circuits with combinational test generation complexity

Optimum retiming of large sequential circuits

A new class of sequential circuits with combinational test generation complexity

Test configurations to enhance the testability of sequential circuits

Sequential circuits with combinational test generation complexity