NDLI: Instruction-set matching and GA-based selection for embedded-processor code generation

Content Provider	IEEE Xplore Digital Library
Author	Shu, J. Wilson, T.C. Banerji, D.K.
Copyright Year	1995
Description	Author affiliation: Dept. of Comput. & Inf. Sci., Guelph Univ., Ont., Canada (Shu, J.; Wilson, T.C.; Banerji, D.K.)
Abstract	The core tasks of retargetable code generation are instruction-set matching and selection for a given application program and a DSP/ASIP processor. In this paper, we utilize a model of target architecture specification that employs both behavioral and structural information, to facilitate this process. The matching method is based on a pattern tree structure of instructions. This tree structure, generated automatically, is implemented by using a pattern queue and a flag table. The matching process is efficient since it bypasses many patterns in the tree which do not match at certain nodes in the DFG of given application program. Two genetic algorithms are implemented for pattern selection: a pure GA which uses standard GA operators, and a GA with backtracking which employs variable-length chromesomes. Optimal or near-optimal pattern selection is obtained in a reasonable period of time for a wide range of application programs.
Starting Page	73
Ending Page	76
File Size	478697
Page Count	4
File Format	PDF
ISBN	0818672285
ISSN	10639667
DOI	10.1109/ICVD.1996.489459
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-01-03
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Digital signal processing Pattern matching Application specific processors Tree data structures Genetic algorithms Computer aided instruction Information science Electronic mail Computational Intelligence Society Computer architecture
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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