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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Leupers, R. Marwedel, P. |
| Copyright Year | 1995 |
| Description | Author affiliation: Dept. of Comput. Sci., Dortmund Univ., Germany (Leupers, R.; Marwedel, P.) |
| Abstract | A main objective in code generation for ASIPs is to develop retargetable compilers in order to permit exploration of different architectural alternatives within short turnaround time. Retargetability requires that the compiler is supplied with a formal description of the target processor. This description is usually transformed into an internal instruction set model, on which the actual code generation operates. In this contribution we analyze the demands on instruction set models for retargetable code generation, and we present a formal instruction set model which meets these demands. Compared to previous work, it covers a broad range of instruction formats and includes a detailed view of inter-instruction restrictions. |
| Starting Page | 77 |
| Ending Page | 80 |
| File Size | 469885 |
| Page Count | 4 |
| File Format | |
| ISBN | 0818672285 |
| ISSN | 10639667 |
| DOI | 10.1109/ICVD.1996.489460 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1996-01-03 |
| Publisher Place | India |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Application specific processors Decoding Computer science Logic Hardware High level languages Registers Digital signal processing Microprogramming Very large scale integration |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electrical and Electronic Engineering Hardware and Architecture |
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