NDLI: A hierarchical register optimization algorithm for behavioral synthesis

Content Provider	IEEE Xplore Digital Library
Author	Katkoori, S. Roy, J. Vemuri, R.
Copyright Year	1995
Description	Author affiliation: Lab. for Digital Design Environ., Cincinnati Univ., OH, USA (Katkoori, S.; Roy, J.; Vemuri, R.)
Abstract	In this work, we address the problem of register optimization that arises during high-level synthesis from hierarchical behavioral specifications containing a hierarchy of modules such as procedures, functions etc. Register optimization (or register sharing) is the process of grouping carriers in the specification such that each group can be safely assigned to a hardware register. Global register optimization by in-line expansion involves flattening the module hierarchy and using a heuristic register optimization procedure on the flattened description. Although in-line expansion leads to near-optimal number of registers, it is time consuming due to the large number of carrier compatibility relationships that must be considered. We present an efficient register optimization algorithm which achieves nearly the same effect of in-line expansion without actually in-line expanding at the specification level. It differs from other techniques as it employs a hierarchical optimization phase which exploits the properties of the module call graph and the information gathered during local carrier life-cycle analysis of each module. Experimental results on a number of examples show that the proposed algorithm produces nearly the same number of registers as in-line expansion based global optimization and is faster by a factor ranging from 1.5 to 18.3.
Starting Page	126
Ending Page	132
File Size	798228
Page Count	7
File Format	PDF
ISBN	0818672285
ISSN	10639667
DOI	10.1109/ICVD.1996.489471
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-01-03
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	High level synthesis Hardware Design optimization Registers Information analysis Minimization methods Algorithm design and analysis Monitoring Contracts Design automation
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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