NDLI: Optimum retiming of large sequential circuits

Content Provider	IEEE Xplore Digital Library
Author	Chakradhar, S.T.
Copyright Year	1995
Description	Author affiliation: Comput. & Commun. Res. Lab., NEC Res. Inst., Princeton, NJ, USA (Chakradhar, S.T.)
Abstract	We present a new, fast algorithm for optimally retiming large sequential circuits under the unit delay model. Our method consists of two main steps: (1) computation of the optimum clock period and (2) computation of a feasible retiming For the optimum clock period. We construct a path graph that has as many vertices as there are flip-flops in the circuit. The path graph also has an additional vertex that corresponds to all primary Inputs and outputs of the circuit. There is an arc from a vertex to another if there is a strictly combinational path between the corresponding flip-flops, primary inputs or outputs. We formulate an integer linear program (ILP) on the path graph to compute the minimum clock period /spl phi//sub opt/ for which the path graph has no critical cycles. An optimum solution to the ILP is determined from the optimum solution of the corresponding linear program (LP) relaxation. We show that /spl phi//sub opt/ is also the optimum clock period for the circuit. After determining the optimum clock period, a feasible retiming for the optimum clock period is obtained using known retiming methods. Experimental results on several large benchmarks and production VLSI circuits show that our method is significantly faster than the best optimal retiming method known to date. Also, optimum retiming results for these benchmark circuits are being presented for the first time.
Starting Page	135
Ending Page	140
File Size	565113
Page Count	6
File Format	PDF
ISBN	0818669055
ISSN	10639667
DOI	10.1109/ICVD.1995.512092
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-01-04
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Sequential circuits Clocks Flip-flops Very large scale integration Logic circuits Logic gates National electric code Delay Production Minimization
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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