NDLI: Parallel simulated annealing strategies for VLSI cell placement

Content Provider	IEEE Xplore Digital Library
Author	Chandy, J.A. Banerjee, P.
Copyright Year	1995
Description	Author affiliation: Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA (Chandy, J.A.; Banerjee, P.)
Abstract	Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a compute-intensive process, and as a result several research efforts have been undertaken to parallelize this algorithm. Most previous parallel approaches to cell placement annealing have used a parallel moves approach. In this paper we investigate two new approaches that have been proposed for generalized parallel simulated annealing but have not been applied to the cell placement problem. Results are presented on the effectiveness of implementations of these algorithms when applied to the cell placement problem. We find that the first, multiple Markov chains, appears to be promising since it uses parallelism to obtain near linear speedups with no loss in quality. The second, speculative computation, while maintaining quality is not suitable since no speedups are achieved due to the specific nature of the cell placement problem. The two algorithms are compared with the parallel moves approach to parallel cell placement.
Starting Page	37
Ending Page	42
File Size	729235
Page Count	6
File Format	PDF
ISBN	0818672285
ISSN	10639667
DOI	10.1109/ICVD.1996.489451
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-01-03
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Simulated annealing Very large scale integration Computational modeling Object oriented modeling Yarn Concurrent computing Algorithm design and analysis Design automation Circuit synthesis Circuit testing
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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