NDLI: A graph based approach to the synthesis of multi-chip module architectures

Content Provider	IEEE Xplore Digital Library
Author	Cherabuddi, R.V. Chen, J. Bayoumi, M.A.
Copyright Year	1995
Description	Author affiliation: Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA (Cherabuddi, R.V.; Chen, J.; Bayoumi, M.A.)
Abstract	We present a graph based approach to the time (performance) constrained synthesis of multi-chip module (MCM) architectures. System-level partitioning is performed using the Stochastic Evolution heuristic, which is an effective heuristic for solving several combinatorial optimization problems. The partitioning cost function models the scheduling/allocation constraints (including interchip buses) in the form of incompatible sets. Supernodes are created using the scheduling/allocation constraints which in turn reduces the search space for the partitioner. Scheduling and resource allocation is performed for the case of time (performance) constrained synthesis and includes modeling of inter-chip buses, multi-cycle operations, pipelined functional units and functional pipelining. Efficient synthesis results are obtained for the high-level synthesis benchmarks in far less CPU time compared to the integer linear programming based model.
Starting Page	192
Ending Page	197
File Size	675598
Page Count	6
File Format	PDF
ISBN	0818672285
ISSN	10639667
DOI	10.1109/ICVD.1996.489483
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-01-03
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	High level synthesis Time factors Computer architecture Cost function Pipeline processing Communication system control Network synthesis Very large scale integration Laboratories Stochastic systems
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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