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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Dasgupta, P.S. Sen, A.K. Nandy, S.C. Bhattacharya, B.B. |
| Copyright Year | 1995 |
| Description | Author affiliation: Comput. Center, Indian Inst. of Manage., Calcutta, India (Dasgupta, P.S.; Sen, A.K.) |
| Abstract | We identify a new problem called geometric bipartitioning that is useful in VLSI layout design. Given a floorplan with rectilinear modules, the problem is to partition the floor by a staircase (monotone increasing) channel from one corner of the floor to its diagonally opposite corner, such that the numbers of modules in the two halves become equal. As the partition is heavily dependent on the geometry of the floorplan, this is quite different from the classical graph bisection problem. This problem can be captured using a weighted permutation graph with integer edge weights, which may be positive, negative or zero; the goal is to find a path between two designated nodes such that the absolute value of the sum of edge weights along the path is minimum. We then show that this problem is NP-complete, and present a heuristic algorithm based on branch-and-bound. Experimental results with benchmarks and randomly generated floorplans reveal that the algorithm produces optimal results quickly most of the time. Geometric bipartitioning problem may find many applications to hierarchical decomposition, floorplanning, and routing. |
| Starting Page | 400 |
| Ending Page | 405 |
| File Size | 707615 |
| Page Count | 6 |
| File Format | |
| ISBN | 0818672285 |
| ISSN | 10639667 |
| DOI | 10.1109/ICVD.1996.489642 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1996-01-03 |
| Publisher Place | India |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Very large scale integration Routing Partitioning algorithms Heuristic algorithms Integrated circuit interconnections Costs Application software Geometry Constraint optimization Delay |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electrical and Electronic Engineering Hardware and Architecture |
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