NDLI: Design for high-speed testability of stuck-at faults

Content Provider	IEEE Xplore Digital Library
Author	Chakraborty, T.J. Agrawal, V.D.
Copyright Year	1995
Description	Author affiliation: AT&T Bell Labs., Princeton, NJ, USA (Chakraborty, T.J.)
Abstract	When tests are applied at the maximum allowable clock frequency or the rated speed, delays of critical paths can be comparable to the clock period. Hence, delayed signal transitions or timing hazards can influence the detection of faults. It is thus possible that a stuck-at fault that is detected by a test applied at slow speed, may not be detected with high speed test application. This paper makes two new contributions. First, we present a new multivalue algebra and a comprehensive test generation algorithm for the previously described dh-robust tests for stuck-at faults. These tests guarantee fault detection at any clock speed up to the rated clock speed of the circuit even when a delay fault is also present. Second, we identify that presence of sequential feedbacks and reconvergent fanouts as the primary obstacle in obtaining the dh-robust tests for a sequential circuits. We propose cycle-free sequential circuits, which may be obtained by partial scan, if necessary, as the design for high-speed testability.
Starting Page	53
Ending Page	56
File Size	441844
Page Count	4
File Format	PDF
ISBN	0818672285
ISSN	10639667
DOI	10.1109/ICVD.1996.489454
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-01-03
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing Circuit faults Clocks Delay Fault detection DH-HEMTs Sequential analysis Sequential circuits Frequency Timing
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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