NDLI: Unified model for on-chip interconnects

Content Provider	IEEE Xplore Digital Library
Author	Sunil Yu Sang-Pil Sim Krishnan, S. Petranovic, D.M. Kwyro Lee Yang, G.Y.
Copyright Year	2004
Description	Author affiliation: Center for Nanoelectronics, Santa Clara Univ., CA, USA (Sunil Yu; Sang-Pil Sim; Krishnan, S.)
Abstract	In this paper, we present a compact unified model for on-chip interconnects, which includes a quasi-3D capacitance model and an effective loop inductance model. To effectively model three-dimensional fringe components in the capacitance model, we propose a novel concept of effective width for a 3D wire, which provides a physics-based approach to decompose any 3D structure into a series of 2D segments. To construct analytic and hierarchical model of loop inductance, an effective loop inductance approach is studied. In particular, we show empirically that high-frequency signal propagating through random signal lines can be approximated by a quasi-TEM mode relationship, leading to a simple way to extract the high-frequency inductance. The capacitance and inductance models are combined into a unified frequency-dependent RLC model describing successfully the wide-band characteristics of on-chip interconnects up to 100GHz. Non-orthogonal wire architecture is also investigated and included in the proposed model. Regarding coupled wire, the impact of resistance matrix on crosstalk noise is studied. The off-diagonal terms of resistance matrix are related to return path, which is important for accurate noise modeling at high frequency. It is shown that the error in crosstalk peak noise can be significant if the return path resistance is ignored.
Starting Page	1026
Ending Page	1031
File Size	1733765
Page Count	6
File Format	PDF
ISBN	078038511X
DOI	10.1109/ICSICT.2004.1436681
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-10-18
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Capacitance Inductance Crosstalk Integrated circuit interconnections Frequency Wire Solid modeling CMOS technology Geometry Low-frequency noise
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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