NDLI: A novel multiphase clock generator based on digital DLL designed for oversampling in transceiver

Content Provider	IEEE Xplore Digital Library
Author	Xi Jianxiong He Lenian Li Haoliang Yan Xiaolang
Copyright Year	2004
Description	Author affiliation: Inst. of VLSI Design, Zhejiang Univ., Hangzhou, China (Xi Jianxiong; He Lenian; Li Haoliang; Yan Xiaolang)
Abstract	This paper describes a novel multiphase clock generator with simplicity, short locking time and low jitter performance. The multiphase clock generator is based on digital delay-locked loop (DLL). The novel digital DLL incorporates lead-lag phase detector and digital controlled delay line (DCDL) with a simple counter to generate equally spaced five-phase clocks. The whole circuit has been simulated by using Cadence's SPECTRE software and TSMC's library of 0.25 /spl mu/n CMOS model. The worst peak-to-peak long-term jitter of the multiphase clocks is less than 23ps at 480MHz. And the locking time is about several clock cycles. It can be perfectly applied in circuit of USB for oversampling in high speed transceiver.
Starting Page	1543
Ending Page	1546
File Size	929890
Page Count	4
File Format	PDF
ISBN	078038511X
DOI	10.1109/ICSICT.2004.1436909
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-10-18
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Transceivers Jitter Phase detection Detectors Digital control Delay lines Counting circuits Circuit simulation Software libraries
Content Type	Text
Resource Type	Article

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