NDLI: A 3.125Gbit/s CMOS clock and data recovery circuit

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2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

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Proceedings. 7th International Conference on Solid-State and Integrated Circuits Technology, 2004.

Volume 3 - 2004

Volume 2 - 2004

2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings - Title

Conference organization

Welcome address [ICSICT 2004]

Conductivity to first SBD of a stress induced leakage path in ultrathin thermal oxides

A review of positive charge formation in gate oxides

A new approach to characterize and predict lifetime of deep-submicron nMOS devices

Interface passivation by deuterium for nanoscale CMOS devices

On the design of tunable high-holding-voltage LVTSCR-based cells for on-chip ESD protection

Study on near-flatband-voltage SILC in ultra-thin plasma nitrided gate oxides

TDDB characteristics of ultra-thin HfN/HfO/sub 2/ gate stack

Hot carrier issues in thin body double-gate MOSFET

RF reliability of MOSFETs subject to electrical stress

Active ESD shunt with transistor feedback to reduce latchup susceptibility or false triggering

Mechanism of negative bias temperature instability for PMOSFET's with thin gate oxide

Interface trap generation on thin SiO/sub 2/ and plasma-nitrided SiO/sub 2/ gate dielectrics under static and dynamic stresses

The statistical analysis of substrate current to soft breakdown in ultra-thin gate oxide n-MOSFETs

An investigation of endurance characteristic using PDO method in FLOTOX EEPROM structures

A new observation of hot-carrier induced interface traps spatial distribution in 0.135 /spl mu/m n-MOSFET by gate-diode method

The board implementation for checking SEU test on memory devices

Influence of fluorine on radiation-induced charge trapping in the SIMOX buried oxides

Radiation response of partially-depleted MOS transistors fabricated in the fluorinated SIMOX wafers

A design model of gate-coupling NMOS ESD protection circuit

Modeling of MEMS reliability in shock environments

Bottom-up silicon nanoelectronics

Advances in Si-based nanotechnology and quantum devices

Quantum-dot cellular automata

Silicon nanocrystal memories

Metal nano-dot memory for high-density non-volatile memory application

Memory effect in Si nanocrystal embedded SiO/sub 2/ films

Spontaneous polarization induced growth of ZnO nanostructures

Charging and Coulomb blockade effects in nanocrystalline Si dots embedded in SiO/sub 2/ matrix

High-density Ge dots grown on Si substrate by modified S-K Method

Preparation of InAs quantum dots on GaAs substrate by metal-organic vapor phase epitaxy using N/sub 2/ as carrier gas

Composition of nanometer-scaled self-assembled SiGe islands

A novel approach to evaluate the carrier effective mass in GeSi quantum dot structure

Recent progress in MOS compact modeling

BSIM5 MOSFET Model

Xsim: unified regional approach to compact modeling for next generation CMOS

Compact modeling for drain current of short-channel MOSFETs including source/drain resistance effect

Extracting the model parameters of non-ideal junctions based on explicit analytical solutions of I-V characteristics

Physics-based exact analytical drain current equation and optimized compact model for long channel MOS transistors

Threshold voltage correction model for quantum short channel

Mobility model of polysilicon thin-film transistor (poly-Si TFT)

Dopant profile extraction by inverse modeling of scanning capacitance microscopy using peak dC/dV

A simple method for effective channel length, series resistance and mobility extraction in deep-submicron MOSFETs

An analytical charge density model comprising 1D quantum mechanical (QM) effect for sub-100nm bulk silicon MOSFETs

Simulation of quantum transport in an ultra-small SOI MOSFET

Gate leakage models for device simulation

Numerical modeling of quantum waveguide device

Sub-100nm strained Si CMOS: device performance and circuit behavior

Quantum effect simulation of SOI MOSFETs considering impact ionization

An accurate and efficient surface scattering model for Monte Carlo device simulation

Monte Carlo simulation of hole non-stationary transports in UTB SOI pMOSFET

Simulation of RTD using quantum hydrodynamic model

Impact of surface traps on downscaled InP/InGaAs DHBTs

Simulation and analysis of the high frequency performances of SiGe HBT with quantum well base region

Investigation on the sources of 2DEG in Al/sub x/Ga/sub 1-x/N/GaN HEMT

Computational investigation of velocity overshoot effects in double gate MOSFETs

A simulation model of body contact structure in PD SOI analogue circuit

Compacted simulation: a new leakage current estimation method

Unified model for on-chip interconnects

New mechanisms governing diffusion in silicon for transistor manufacture

An efficient algorithm for 3-D interconnect capacitance extraction considering the floating dummy-fills

Efficient 3-D interconnect capacitance extraction based on direct solving techniques for system with multiple right-hand sides

3D-IC performance computing of single-gate SOI CMOS inverter

Modeling the effects of patterning error on MOSFET

Defects in ion implantation and annealing studied by atomistic model

Multiple ion implantation simulation by TSUPREM-IV

A new damage model for ion implantation simulation with molecular dynamics method

A content-driven model-based OPC tool

A study of parametric yield estimation by uniform design sampling

3D simulation of profile evolution in silicon DRIE

A two dimensional dynamic cellular automata model for simulation of photoresist etching process

Correction simulation for simultaneous suppression of overlaps and side-lobes in attenuated PSM lithography

Circuit model parameter generation with TCAD simulation

A novel analytical thermal model for temperature estimation of multilevel ULSI interconnects

Elmore delay estimation of two adjacent coupling interconnects

Simulation of etched profile based on singular point splitting algorithm

Reaction mechanism of ZrCl/sub 4/ with Ge/Si(100)-(2/spl times/1): A density functional theory study of initial stage of ZrO/sub 2/ atomic layer deposition on SiGe alloy surface

Yield modeling based on circular defect size and a real defect rectangular degree

An improved statistical modeling method based on silicon plant back-end ET data

Noise modeling of Si and SiGe devices

MOSFET modeling for RF-circuit simulation

An overview of device modeling in bridging manufacturing and design for RF applications

Non-quasi-static modeling of heterojunction bipolar transistors

An analytical high frequency noise model for hot-carrier stressed MOSFETs

CMOS transistor mismatch model with temperature effect for HSPICE and SPECTRE

Mathematical basis of the expressions used by the integral function method for the determination of nonlinear harmonic distortion in devices and circuits

Nonlinear distortion simulation algorithm with capability of distortion diagnosis for analog and RF integrated circuits

A new closed-form expression for capacitive coupling of lossy substrate

An improved methodology for analysis of s-parameter measurements on substrate crosstalk test structures

Boundary element method for substrate resistance calculation

Small signal non-quasi-static model for AlGaN/GaN MODFETs

Impact of leakage currents on MOSFET noise performance in deep sub-micron regime

Advanced compact modeling of logic devices toward CMOS scaling limits

Poisson-Boltzmann solutions to the one-dimensional oxide-silicon-oxide system

Analytical thermal model for silicon-on-insulator MOSFET structures

Scaling properties of GOI MOSFETs in nano scale by full band Monte Carlo simulation

A physics based analytical model of undoped body MOSFETs

A compact, continuous analytic I-V model for surrounding-gate MOSFETs

Three dimensional analytical subthreshold model for non-rectangular cross-section FinFETs

Analytical model for the threshold voltage of dual material gate (DMG) partially depleted SOI MOSFET and evidence for reduced short-channel effects

TDCIV extraction of dopant-impurity concentration and oxide thickness in ultrathin gate oxide MOS transistors

Modeling the effects of concentration-dependent carrier mobilities and self-heating on the resistance of thermal sensor built on thin silicon on insulator

An improved strained-Si on Si/sub 1-x/Ge/sub x/ MOSFET mobility model

Analog/mixed-signal and RF integrated circuit technologies for wireless communications

A full-monolithic LNA in 0.18/spl mu/m SiGe: performance variation due to ESD protection

A bumpy journey with GaAs IC foundries in Taiwan and new perspectives of HBT technology readiness for wireless communications in Asia Pacific market

Recent advances in CDMA power amplifier module developments

Ultralow-voltage MTCMOS/SOI technology for batteryless mobile system

A new 5.5GHz LNA with gain control and turn-off control for dual-band WLAN systems

A 5GHz LNA with new compact gain controllable active balun for ISM band applications

An RF CMOS differential negative resistance for Q-enhancement

A high phase accuracy, low amplitude mismatch quadrature LO driver

A concurrent 0.18-/spl mu/m CMOS self-biased dual-band driver amplifier for IEEE 802.11 a/b/g

A high bandwidth and wide dynamic range optical receiver

A noise model for the analog correlator

CMOS RF IC design challenges

Single chip RF transceiver for PHS (Xiao-Ling-Tong) phone

Integration of RF front-end modules in cellular handsets

Meeting the design challenges in modern RFCMOS technology

A new 0.25-/spl mu/m CMOS doubly balanced sub-harmonic mixer for 5-GHz ISM band direct conversion receiver

A novel image rejection CMOS mixer using T-structure filter

A novel technique to improve amplitude imbalance in mixers

Low cost K-band CPW rat-race mixer

A 5-GHz CMOS VCO for IEEE 802.11a WLAN application

A 4.8GHz CMOS fully-integrated LC balanced oscillator with symmetry noise filtering technique

Differentially tuned LC-VCO using modified anti-parallel structure

A 1.8-2GHz VCO with automatic compensation for bond wire inductance variation

A 2.4 GHz fully integrated CMOS LC VCO

Design of CMOS high speed self-regulating VCO using negative skewed delay scheme

Application-oriented platform-based SoC design technology

An enhanced, system-centric, fully hierarchical design method to enable nanometer system-on-chip IC development

Non-contact inter-chip data communications technology for system in a package

SOC for telephone terminal with SMS support

Design of portable infrared business card exchange system on chip

Constraint-based watermarking technique for hard IP core protection in physical layout design level

Implementation of DSR algorithm using VHDL in wireless ad-hoc network

A design approach for GALS based systems-on-chip

An improved DMA controller for high speed data transfer in MPU based SOC

Micro-architecture optimization of THUMP105 SOC implementation

The design of an IEEE802.11 WLAN hardware MAC

The implementation of an out-of-order execution floating point unit

An embedded CMOS voltage reference IP core

A PCI target device with re-reusing PCI AD bus

Integrate binary mapping into task scheduling for hardware/software partitioning

A generic interface modeling approach for SOC design

Test scheduling for core-based SOCs

Microsystems dedicated to wireless multichannel monitoring and microstimulation: design, test and packaging

Power management for modern VLSI loads using dynamic voltage scaling

Digital domain time amplification in CMOS process

Overview of mixed signal methodology for digital full-chip design/verification

A 1.8V CMOS fourth-order Gm-C bandpass sigma-delta modulator dedicated to front-end ultrasonic receivers

A 3.125Gbit/s CMOS clock and data recovery circuit

A temperature independent current reference in ROIC

Correlated double sample design for CMOS image readout IC

The study of dual-window random addressable ROIC

A novel 1.8V rail-to-rail CMOS operational amplifier

An op-amp with novel push-pull output stage for IRFPA ROIC

A high speed CMOS amplifier with active feedforward compensation for contactless card reader

Analysis and design of fully differential gain-boosted telescopic cascode opamp

A dual complex pole-zero cancellation compensation mode for three-stage amplifier

Design of ultra-low voltage op amp based on quasi-floating gate transistors

1.25 Gb/s low power CMOS limiting amplifier for optical receiver

A CMOS hybrid control mode DC-DC buck converter for embedded system

High-performance frequency dividers utilizing differential locking

Fingerprint sensor technology - sensor structure/chip, sensing scheme, and system

Analysis and design of 5GHz phase locked loops

A low power, fast-switching frequency synthesizer of 5.2GHz WLANs

High frequency, low power frequency divider with quadrature outputs and low added phase noise

A monolithic 1 GHz 0.6/spl mu/m CMOS low jitter PLL

1GHz monolithic high spectrum purity fractional-N frequency synthesizer with a 3-b third-order delta-sigma modulator

A CMOS digital PLL with improved locking

A generalized MASH architecture in fractional-N synthesizer

A stack-mode low power prescaler in ISM band ASK receiver

Frequency characteristic analysis and design of high speed current-steering CMOS digital-to-analog converter

A 10-bit 100MSPS 0.35 /spl mu/m Si CMOS pipeline ADC

A 10-bit 20-Msample/s 49mW CMOS pipelined A/D converter

Design of a CPPLL-based clock multiplier for USB hub

Design and optimization of an integrated 1GHz PLL IP for microprocessors

Pulsewidth control loop circuit using combined charge pumps and miller scheme

A novel multiphase clock generator based on digital DLL designed for oversampling in transceiver

A 2.5 GHz CMOS dual-modulus prescaler for RF frequency synthesizer

A low noise current-controlled oscillator with high control linearity

A CMOS charge pump with a novel structure in PLL

A 5V 8b 40MSample/s pipelined analog-to-digital converter

A CMOS 10-bit low-power pipelined A/D converter

A dynamic CMOS comparator with high precision and resolution

A high sensitivity capacitive fingerprint sensor with double sensing plates

A dual-mode serial link transmitter with controlled slew rate

Hot swap controller and its control strategy design

A precise compensated bandgap reference without resistors

An analog fuzzy processor using neuron-MOS technology

CMOS design of analog neuro-fuzzy system with improved circuits

[Inside back cover - blank]

ISBN 0-7803-8511-X [Back Cover]

Volume 1 - 2004

2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)

1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)

Proceedings of 4th International Conference on Solid-State and IC Technology

A 3.125Gbit/s CMOS clock and data recovery circuit

Content Provider	IEEE Xplore Digital Library
Author	Guo Gan Huang Lin Ye Jinghua Chen Yihui Hong Zhiliang
Copyright Year	2004
Description	Author affiliation: ASIC & Syst. State Key Lab., Fudan Univ., Shanghai, China (Guo Gan; Huang Lin; Ye Jinghua; Chen Yihui; Hong Zhiliang)
Abstract	A 3.125Gbit/s clock and data recovery (CDR) circuit is described. The circuit adopts parallel structure to recover clock from high-speed data stream. The working clock is reduced by this method and lower power is achieved. Timing jitter has been considered carefully and the loop parameters are optimized to reduce the output jitter. The circuit is designed with 0.18/spl mu/m CMOS process: the simulated function and performance meet the requirements and the core power dissipation is 56mW.
Starting Page	1429
Ending Page	1432
File Size	1358127
Page Count	4
File Format	PDF
ISBN	078038511X
DOI	10.1109/ICSICT.2004.1436857
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-10-18
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Circuits Frequency Jitter Ethernet networks Bandwidth CMOS process Phase locked loops Voltage-controlled oscillators Gallium nitride
Content Type	Text
Resource Type	Article

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