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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Thorbeck, T. Zimmerman, N. |
| Copyright Year | 2011 |
| Description | Author affiliation: Atomic Physics Division, NIST, USA (Zimmerman, N.) || Department of Physics, University of Maryland, USA (Thorbeck, T.) |
| Abstract | Moving to a three dimensional architecture, such as finFETs (field effect transistor), tri-gate FETS or nanowires, will allow semiconductor devices to scale for a few more nodes. Using the third dimension, these devices offer the same surface area but take up less space on the wafer, at the cost of a possible increase in sensitivity to non-idealities. Smaller devices are likely to be more sensitive to random charged defects. A 3D channel has an increased potential for local strains due to the oxide and the gates compared to a 2D device. Since both charged defects and strain change the surface potential in the channel, these effects could change the threshold voltage. Additionally, local changes in the stress cause local changes in the mobility of the channel. So to improve device uniformity, a technique to determine the possible causes of a surface potential fluctuation would be useful. |
| Starting Page | 1 |
| Ending Page | 2 |
| File Size | 469773 |
| Page Count | 2 |
| File Format | |
| ISBN | 9781457717550 |
| e-ISBN | 9781457717567 |
| DOI | 10.1109/ISDRS.2011.6135171 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-12-07 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Logic gates Wires Strain Quantum dots Quantum capacitance Electric potential |
| Content Type | Text |
| Resource Type | Article |
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