NDLI: Design of a computational nonvolatile RAM for a greedy energy-efficient VLSI processor

Content Provider	IEEE Xplore Digital Library
Author	Mochizuki, A. Yube, N. Hanyu, T.
Copyright Year	2015
Description	Author affiliation: Res. Inst. of Electr. Commun., Tohoku Univ., Sendai, Japan (Mochizuki, A.; Yube, N.; Hanyu, T.)
Abstract	A computational nonvolatile RAM (C-NVRAM), where magneto-resistive random access memory with spin-transfer torque magnetic tunnel junctions (STT-MTJs) is used as an on-chip storage element, combined with bit-parallel arithmetic modules is proposed for a greedy energy-efficient VLSI processors in the wide range of consumer electronics and mobile applications such as internet-of-things. A judicious combination of bit-serial/word-parallel (at a C-NVRAM) and bit-parallel processing manners makes the calculation cycles reduced in parallel computing such as an image processing. Moreover, since data-access rate of the MTJ-based nonvolatile memory is negligible (is only 1/104 percent of memory cell array), its power dissipation is dominated by its static power dissipation. Therefore, the use of nonvolatile memory makes the total power reduced greatly. As a typical application, it is demonstrated in parallel image processing with 8-bit-intensity 256×256 pixels that the energy (computing-time-power-dissipation product) of the proposed hardware is less than 1/15 in comparison with that of the corresponding CMOS-only-based one under a 90nm-CMOS/100nm-MTJ process technologies.
Sponsorship	IEEE
Starting Page	003283
Ending Page	003288
File Size	593676
Page Count	6
File Format	PDF
e-ISBN	9781479917624
DOI	10.1109/IECON.2015.7392606
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-11-09
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Random access memory Computer architecture Microprocessors Nonvolatile memory Leakage currents Magnetic tunneling Energy efficiency leakage current reduction logic-in-memory hardware accelerator C-RAM STT-MRAM magnetic-tunneling-junction device SIMD parallel computing power gating
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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