NDLI: Cost-efficiency code generation approach of software pipelining for FPGA architectures

Content Provider	IEEE Xplore Digital Library
Author	Lin Shaodu Zheng Hongbin Cheng Lin Chen Dihu Wang Zixin
Copyright Year	2010
Description	Author affiliation: School of Physics and Engineering, Sun Yat-sen University, Guangzhou 510275, China (Lin Shaodu; Zheng Hongbin; Cheng Lin; Chen Dihu; Wang Zixin)
Abstract	Software pipelining is an optimization algorithm, which is unrolling iteration to improve the executive efficiency by loop-unrolled technology. As the loop is unrolled by more times, we will get large bigger codes that we need the hardware resource sharply increased. To solve the problem which needs large hardware resource because of unrolling the loop, we propose a new approach which is reconstructing state to share state resource and establishing the finite state machine model of software pipelining. It is the cost-efficiency code generation approach of software pipelining. The model can fulfill to reuse hardware resource and need less hardware resource by using the FSM to control the reusing of kernel codes of the pipelining technology.
Starting Page	4459
Ending Page	4462
File Size	492897
Page Count	4
File Format	PDF
ISBN	9781424476169
e-ISBN	9781424476183
DOI	10.1109/ICISE.2010.5688885
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-12-04
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	State reconstruction IEEE Computer Society Software algorithms FPGA Computer architecture Software Hardware Finite state machine(FSM) Software pipelining Field programmable gate arrays Pipeline processing
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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