NDLI: Parallel matrix algorithm autotuner on multi-core architecture

Content Provider	IEEE Xplore Digital Library
Author	Zhang Ji-Lin Ren Yong-Jian Zhang Wei Xu Xiang-Hua Wan Jian Du Jiang-Hui
Copyright Year	2010
Description	Author affiliation: School of Information Engineering, University of Science and Technology Beijing, 100083, China (Du Jiang-Hui) \|\| School of Computer, Hangzhou Dianzi Unviersity, 310018, China (Zhang Ji-Lin; Ren Yong-Jian; Zhang Wei; Xu Xiang-Hua; Wan Jian)
Abstract	This paper develops a performance autotuner of the parallel sparse matrix multiplication algorithm. This autotuner can utilize the cache characters of multicore computers. It can optimize the value of performance parameters in multicore and achieve the better performance of parallel matrix multiplication algorithm. This paper proposes a parallel matrix multiplication algorithm by Using the CSR compression and cache blocking technology. The cache blocking parameters are optimized to get the better performance. From the matrix experiments, we can consult that the autotuner system can achieve the sparse matrix multiplication algorithm better performance on the multicore hardware.
Starting Page	5227
Ending Page	5230
File Size	326076
Page Count	4
File Format	PDF
ISBN	9781424476169
e-ISBN	9781424476183
DOI	10.1109/ICISE.2010.5691457
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-12-04
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Multicore Multicore processing Matrix multiplication Conferences IEEE Computer Society Press Autotuner Parallel Sparse matrices Kernel Optimization
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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