NDLI: PipeRoute: a pipelining-aware router for reconfigurable architectures

Content Provider	IEEE Xplore Digital Library
Author	Sharma, A. Ebeling, C. Hauck, S.
Copyright Year	1982
Abstract	We present a pipelining-aware router for fieldprogrammable gate arrays (FPGAs). The problem of routing pipelined signals is different from the conventional FPGA routing problem. The two-terminal N/sub D/ pipelined routing problem is to find the lowest cost route between a source and sink that goes through at least N (N/spl ges/1) distinct pipelining resources. In the case of a multiterminal pipelined signal, the problem is to find a minimum spanning tree (MST) that contains sufficient pipelining resources such that pipelining constraints at each sink are satisfied. In this paper, we first present an optimal algorithm for finding a lowest cost 1/sub D/ route. The optimal 1/sub D/ algorithm is then used as a building block for a greedy two-terminal N/sub D/ router. Next, we discuss the development of a multiterminal routing algorithm (PipeRoute) that effectively leverages both the 1/sub D/ and N/sub D/ routers. Finally, we present a preprocessing heuristic that enables the application of PipeRoute to pipelined FPGA architectures. PipeRoute's performance is evaluated by routing a set of benchmark netlists on the reconfigurable pipelined datapath (RaPiD) architecture. Our results show that the architecture overhead incurred in routing netlists on RaPiD is less than 20%. Further, the results indicate a possible trend between the architecture overhead and the percentage of pipelined signals in a netlist.
Sponsorship	IEEE Council on Electronic Design Automation IEEE Circuits and Systems Society
Starting Page	518
Ending Page	532
Page Count	15
File Size	482511
File Format	PDF
ISSN	02780070
Volume Number	25
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-03-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Reconfigurable architectures Field programmable gate arrays Routing Pipeline processing Clocks Logic Integrated circuit interconnections Computer architecture Cost function Automation routing Design automation field-programmable gate arrays (FPGA) reconfigurable architectures
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Electrical and Electronic Engineering Software

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Device and Architecture Cooptimization for FPGA Power Reduction

TRACER-fpga: a router for RAM-based FPGA's

Resource allocation for coarse-grain FPGA development

FPGA Architecture Optimization Using Geometric Programming

Slack Allocation and Routing to Improve FPGA Timing While Repairing Short-Path Violations

Interconnect estimation for FPGAs

Application-independent testing of FPGA interconnects

Field Programmability of Supply Voltages for FPGA Power Reduction

Novel Computing Architectures

PipeRoute: a pipelining-aware router for reconfigurable architectures

Similar Documents

Device and Architecture Cooptimization for FPGA Power Reduction

TRACER-fpga: a router for RAM-based FPGA's

Resource allocation for coarse-grain FPGA development

FPGA Architecture Optimization Using Geometric Programming

Slack Allocation and Routing to Improve FPGA Timing While Repairing Short-Path Violations

Interconnect estimation for FPGAs

Application-independent testing of FPGA interconnects

Field Programmability of Supply Voltages for FPGA Power Reduction

Novel Computing Architectures

PipeRoute: a pipelining-aware router for reconfigurable architectures