NDLI: Characterization of radiation-induced SRAM and logic soft errors from 0.33V to 1.0V in 65nm CMOS

Content Provider	IEEE Xplore Digital Library
Author	Pawlowski, R. Crop, J. Cho, M. Tschanz, J. De, V. Fairbanks, T. Quinn, H. Borkar, S. Chiang, P.Y.
Copyright Year	2014
Description	Author affiliation: Intel Corp., Hillsboro, OR, USA (Cho, M.; Tschanz, J.; De, V.; Borkar, S.) \|\| Los Alamos Nat. Lab., Los Alamos, NM, USA (Fairbanks, T.; Quinn, H.) \|\| Sch. of EECS, Oregon State Univ., Corvallis, OR, USA (Pawlowski, R.; Crop, J.; Chiang, P.Y.)
Abstract	This work details a process-portable test chip, fabricated in 65nm CMOS, specifically designed to measure radiation-induced soft error rate (SER) during operation at near-threshold. A variety of SRAM, register file (RF), and digital logic test structures are included that provide a comprehensive assessment of circuit sensitivities to radiation at low $V_{DD}.$ Neutron irradiation measurements of SRAM/RF show a 6.45x increase in SER when $V_{DD}$ is lowered from 1.0V to 0.33V, and a 2.6x increase in multi-bit upsets. Alpha bombardment of digital logic tests demonstrates the effectiveness of this test chip platform in characterizing the relationship between SER and different circuit characteristics when operating at low $V_{DD}.$
Sponsorship	IEEE Electron Dev. Soc.
Starting Page	1
Ending Page	4
File Size	520258
Page Count	4
File Format	PDF
ISBN	9781479932863
DOI	10.1109/CICC.2014.6946138
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-09-15
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Error analysis Inverters Random access memory Neutrons Integrated circuit modeling CMOS integrated circuits Market research soft errors logic memory near-threshold reliability
Content Type	Text
Resource Type	Article

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