NDLI: Reconfigurable blocker-resilient receiver with concurrent dual-band carrier aggregation

Content Provider	IEEE Xplore Digital Library
Author	Run Chen Hashemi, H.
Copyright Year	2014
Description	Author affiliation: Dept. of Electr. Eng. - Electrophys., Univ. of Southern California, Los Angeles, CA, USA (Run Chen; Hashemi, H.)
Abstract	A reconfigurable software-defined radio receiver supporting dual-band carrier aggregation is demonstrated in a 65nm LP CMOS technology. A front-end filter, leveraging both the input impedance and voltage transfer functions of an N-path filter, can be configured either as a parallel bandpass or a series notch filter. The dual-band carrier aggregation is achieved by combing a conventional N-path filter with complex signal processing at baseband. The center frequencies of the desired two RF bands can be separated anywhere between 0 to +100 MHz within 0.1 to 1 GHz. The front-end notch filter configuration improves the blocker tolerance by 15 dB compared to the bandpass filter configuration at the expense of noise figure increase by 2 to 3.5 dB.
Sponsorship	IEEE Electron Dev. Soc.
Starting Page	1
Ending Page	4
File Size	7354419
Page Count	4
File Format	PDF
ISBN	9781479932863
DOI	10.1109/CICC.2014.6946016
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-09-15
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Receivers Radio frequency Baseband Clocks Impedance Frequency measurement Transfer functions N-path filter receiver CMOS software-defined radio carrier aggregation reconfigurable
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Reconfigurable Receiver With Radio-Frequency Current-Mode Complex Signal Processing Supporting Carrier Aggregation

Dual-Carrier Aggregation Receiver With Reconfigurable Front-End RF Signal Conditioning

Concurrent dual-band receiver for spectrum aggregation system

A double bandpass N-path filter for LTE carrier aggregation receivers in 28nm CMOS

A 130nm CMOS 100Hz–6GHz reconfigurable Vector Signal Analyzer and Software-Defined Receiver

A reconfigurable spatial moving average filter in sampler-based discrete-time receiver

A 1.8 dB NF Blocker-Filtering Noise-Canceling Wideband Receiver With Shared TIA in 40 nm CMOS

A 65 nm CMOS Quad-Band SAW-Less Receiver SoC for GSM/GPRS/EDGE

A Widely-Tunable Reconfigurable CMOS Analog Baseband IC for Software-Defined Radio

Reconfigurable blocker-resilient receiver with concurrent dual-band carrier aggregation

Similar Documents

Reconfigurable Receiver With Radio-Frequency Current-Mode Complex Signal Processing Supporting Carrier Aggregation

Dual-Carrier Aggregation Receiver With Reconfigurable Front-End RF Signal Conditioning

Concurrent dual-band receiver for spectrum aggregation system

A double bandpass N-path filter for LTE carrier aggregation receivers in 28nm CMOS

A 130nm CMOS 100Hz–6GHz reconfigurable Vector Signal Analyzer and Software-Defined Receiver

A reconfigurable spatial moving average filter in sampler-based discrete-time receiver

A 1.8 dB NF Blocker-Filtering Noise-Canceling Wideband Receiver With Shared TIA in 40 nm CMOS

A 65 nm CMOS Quad-Band SAW-Less Receiver SoC for GSM/GPRS/EDGE

A Widely-Tunable Reconfigurable CMOS Analog Baseband IC for Software-Defined Radio

Reconfigurable blocker-resilient receiver with concurrent dual-band carrier aggregation