NDLI: Technology-design-manufacturing co-optimization for advanced mobile SoCs

Content Provider	IEEE Xplore Digital Library
Author	Yeap, Geoffrey
Copyright Year	2014
Description	Author affiliation: Qualcomm Technologies Inc., 5775 Morehouse Drive, San Diego, CA 92121 (Yeap, Geoffrey)
Abstract	How to maintain the Moore's Law scaling beyond the 193 immersion resolution limit is the key question semiconductor industry needs to answer in the near future. Process complexity will undoubtfully increase for 14nm node and beyond, which brings both challenges and opportunities for technology development. A vertically integrated technology-design-manufacturing co-optimization flow is desired to better address the complicated issues new process changes bring. In recent years smart mobile wireless devices have been the fastest growing consumer electronics market. Advanced mobile devices such as smartphones are complex systems with the overriding objective of providing the best user-experience value by harnessing all the technology innovations. Most critical system drivers are better system performance/power efficiency, cost effectiveness, and smaller form factors, which, in turns, drive the need of system design and solution with More-than-Moore innovations. Mobile system-on-chips (SoCs) has become the leading driver for semiconductor technology definition and manufacturing. Here we highlight how the co-optimization strategy influenced architecture, device/circuit, process technology and package, in the face of growing process cost/complexity and variability as well as design rule restrictions.
Starting Page	1
Ending Page	8
File Size	674358
Page Count	8
File Format	PDF
ISBN	9781479932863
DOI	10.1109/CICC.2014.6946000
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-09-15
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Mobile communication System-on-chip Optimization Metals Performance evaluation Logic gates Standards local interconnect Mobile SoCs design-technology co-optimization design rule double patterning
Content Type	Text
Resource Type	Article

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