NDLI: AMD SOC power management: Improving performance/watt using run-time feedback

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2015 IEEE Custom Integrated Circuits Conference (CICC)

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference

Welcome from the CICC committee

Steering committee

Educational sessions

Table of contents

A 8.125–15.625 Gb/s SerDes using a sub-sampling ring-oscillator phase-locked loop

Wideband flexible-reach techniques for a 0.5–16.3Gb/s fully-adaptive transceiver in 20nm CMOS

Design considerations for low-power analog front ends in full-duplex 10GBASE-T transceivers

A HomePlugAV SoC in 40nm CMOS technology

A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology

A 0.18-μm CMOS fully integrated 0.7–6 GHz PLL-based complex dielectric spectroscopy system

Matching the power density and potentials of biological systems: A 3.1-nW, 130-mV, $0.023-mm^{3}$ pulsed 33-GHz radio transmitter in 32-nm SOI CMOS

A 239–281GHz Sub-THz imager with 100MHz resolution by CMOS direct-conversion receiver with on-chip circular-polarized SIW antenna

Advances in high-speed continuous-time delta-sigma modulators

A 11μW 250 Hz BW two-step incremental ADC with 100 dB DR and 91 dB SNDR for integrated sensor interfaces

An all-digital PWM-based ΔΣ ADC with an inherently matched multi-bit quantizer

A VCO-based current-to-digital converter for sensor applications

Lookup-table-based background linearization for VCO-based ADCs

A 1.2 V 2.64 GS/s 8bit 39 mW skew-tolerant time-interleaved SAR ADC in 40 nm digital LP CMOS for 60 GHz WLAN

A 160 MS/s, 11.1 mW, single-channel pipelined SAR ADC with 68.3 dB SNDR

Design for test of a mm-Wave ADPLL-based transmitter

A low-leakage, hybrid ESD power supply clamp in 65nm CMOS technology

A test circuit based on a ring oscillator array for statistical characterization of Plasma-Induced Damage

Impact of random telegraph noise on CMOS logic circuit reliability

TCAD structure synthesis and capacitance extraction of a voltage-controlled oscillator using automated layout-to-device synthesis methodology

The challenges of analog circuits on nanoscale technologies

Technology-design-manufacturing co-optimization for advanced mobile SoCs

New System-in-Package (SiP) Integration technologies

Reliability modeling of HK MG technologies

Understanding the regenerative comparator circuit

A 9-bit 215-MS/s folding-flash time-to-digital converter based on redundant remainder number system

A $0.010mm^{2}$ 9.92psrms low tracking jitter pixel clock generator with a divider initializer and a nearest phase selector in 28nm CMOS technology

A −115dB PSRR CMOS bandgap reference with a novel voltage self-regulating technique

A 500nA quiescent current, trim-free, ±1.75% absolute accuracy, CMOS-only voltage reference based on anti-doped N-channel MOSFETs

A 5.8nW, 45ppm/°C on-chip CMOS wake-up timer using a constant charge subtraction scheme

Stochastic testing simulator for integrated circuits and MEMS: Hierarchical and sparse techniques

PPV-based modeling and event-driven simulation of injection-locked oscillators in SystemVerilog

Efficient per-element distortion contribution analysis via Harmonic Balance adjoints

The role of translational circuits in RF receiver design

A 16-band channelizer employing harmonic rejection mixers with enhanced image rejection

A baseband technique for automated LO leakage suppression achieving < −80dBm in wideband passive mixer-first receivers

Multi-mode cellular transceivers for LTE and LTE-Advanced

Reconfigurable blocker-resilient receiver with concurrent dual-band carrier aggregation

Energy scaling in multi-tiered sensing systems through compressive sensing

Robust, reconfigurable, and power-efficient biosignal recording systems

A 32-Gb/s 9.3-mW CMOS equalizer with 0.73-V supply

A 50–64 Gb/s serializing transmitter with a 4-tap, LC-ladder-filter-based FFE in 65-nm CMOS

An 8GHz first-order frequency synthesizer based on phase interpolation and quadrature frequency detection in 65nm CMOS

A 12.5-Gb/s self-calibrating linear phase detector-based CDR using 0.18μm SiGe BiCMOS

A 6.5Mb/s to 11.3Gb/s continuous-rate clock and data recovery

NEEDS: Moving nanoscience to nanotechnology

Optimization and modeling of resonant clocking inductors for the $POWER8^{TM}$ microprocessor

Virtual de-embedding study for the accurate extraction of Fin FET gate resistance

Modeling of resistance in FinFET local interconnect

Compact modeling of LDMOS working in the third quadrant

Directions in future of SRAM with QDR-WideIO for high performance networking applications and beyond

A 16kB tile-able SRAM macro prototype for an operating window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS

HTOL SRAM Vmin shift considerations in scaled HKMG technologies

A 1.1V 2y-nm 4.35Gb/s/pin 8Gb LPDDR4 mobile device with bandwidth improvement techniques

Exploiting error-correcting codes for cache minimum supply voltage reduction while maintaining coverage for radiation-induced soft errors

A two-step 5b logarithmic ADC with minimum step-size of 0.1% full-scale for MLC phase-change memory readout

Progress and future challenges of silicon carbide devices for integrated circuits

Robust design and experimental demonstrations of carbon nanotube digital circuits

Design Technology co-optimization for N10

A new wave of CMOS power amplifier innovations: Fusing digital and analog techniques with large signal RF operations

A mm-wave class-E 1-bit power modulator

A millimeter-wave tunable transformer-based dual-antenna duplexer with 50 dB isolation

A 1.6–2.2GHz 23dBm low loss integrated CMOS duplexer

POWER8 design methodology innovations for improving productivity and reducing power

AMD SOC power management: Improving performance/watt using run-time feedback

A 0.42V Vccmin ASIC-compatible pulse-latch solution as a replacement for a traditional master-slave flip-flop in a digital SOC

Thermal modeling methodology for efficient system-level thermal analysis

MBus: A 17.5 pJ/bit/chip portable interconnect bus for millimeter-scale sensor systems with 8 nW standby power

Highly energy-efficient and quality-tunable inexact FFT accelerators

Enabling flexible datacenter interconnect networks with WDM silicon photonics

CMOS (Sub)-mm-Wave System-on-Chip for exploration of deep space and outer planetary systems

A unified framework for capacitive series-parallel DC-DC converter design

A 45-ratio recursively sliced series-parallel switched-capacitor DC-DC converter achieving 86% efficiency

Conductance modulation techniques in switched-capacitor DC-DC converter for maximum-efficiency tracking and ripple mitigation in 22nm Tri-gate CMOS

High power-density, hybrid inductive/capacitive converter with area reuse for multi-domain DVS

Inverting buck-boost DC-DC converter for mobile AMOLED display with real-time self-tuned minimum power-loss tracking scheme

An analog optimum torque control IC for a 200W wind energy conversion system with over 99% MPPT accuracy, 1.7% THDi and 0.99 power factor

An ultra-low power power management unit with −40dB switching-noise-suppression for a 3×3 thermoelectric generator array with 57% maximum end-to-end efficiency

A 10mV-input boost converter with inductor peak current control and zero detection for thermoelectric energy harvesting

A 33μW/node Duty Cycle Controlled HBC Transceiver system for medical BAN with 64 sensor nodes

An energy harvesting 2×2 60GHz transceiver with scalable data rate of 38-to-2450Mb/s for near range communication

A 52% tuning range QVCO with a reduced noise coupling scheme and a minimum FOMT of 196dBc/Hz

A 350 mV, 5 GHz class-D enhanced swing quadrature VCO in 65 nm CMOS with 198.3 dBc/Hz FoM

A multi-phase sub-harmonic injection locking technique for bandwidth extension in silicon-based THz signal generation

An 85–225MHz Chebyshev-II active-RC BPF with programmable BW and CF achieving over 30dBm IIP3 in 40nm CMOS

A high gain operational amplifier via an efficient conductance cancellation technique

High linearity PVT tolerant 100MS/s rail-to-rail ADC driver with built-in sampler in 65nm CMOS

A 1.2V 110-MHz-UGB differential class-AB amplifier in 65nm CMOS

A stereo 110 dB multi-rate audio ΔΣ DAC with Class-G headphone driver

An open-loop class-D audio amplifier with increased low-distortion output power and PVT-insensitive EMI reduction

A 105dBA SNR, 0.0031% THD+N filterless class-D amplifier with discrete time feedback control in 55nm CMOS

Circuit techniques for miniaturized biomedical sensors

A mm-sized implantable device with ultrasonic energy transfer and RF data uplink for high-power applications

A multiple-output fixed current stimulation ASIC for peripherally-implantable neurostimulation system

Calibrated time-interleaved high-speed ADCs

Miniaturized energy-harvesting piezoelectric chargers

High-performance analog/mixed-signal characterization techniques

Introduction to design considerations of DRAM memory controllers

Advanced modeling and simulation of state-of-the-art high-speed I/O interfaces

Reconfigurable SDR front-end techniques

Recent developments in RF receivers

A robust parasitic-insensitive successive approximation capacitance-to-digital converter

Configurable incremental sigma-delta ADC for DC measure and audio conversion

A hybrid SAR-VCO ΔΣ ADC with first-order noise shaping

A 0.45mW 12b 12.5MS/s SAR ADC with digital calibration

A voltage-scalable 10-b pipelined ADC with current-mode amplifier

A supply-scalable differential amplifier with pulse-controlled common-mode feedback

Low drain voltage S/H type PWM LED current driver for BLU in mobile LCD

A 1.6nJ/bit, 19.9μA peak current fully integrated $2.5mm^{2}$ inductive transceiver for volume-constrained microsystems

A fully integrated electroencephalogram (EEG) analog front-end IC with capacitive input impedance boosting loop

A 27μW subcutaneous wireless biosensing platform with optical power and data transfer

3D multi-gesture sensing system for large areas based on pixel self-capacitance readout using TFT scanning and frequency-conversion circuits

A 0.4 V 75 kbit SRAM macro in 28 nm CMOS featuring a 3-adjacent MBU correcting ECC

Independent N and P process monitors for body bias based process corner correction

A tri-stack buck converter with gate coupling control (GCC) and quasi adaptive dead time control (QADTC)

A fully-integrated, 90% peak efficiency, 0.99 power factor, AC-DC LED Driver with on-chip direct-AC-connect series startup pre-regulator

A 3.15pJ/cyc 32-bit RISC CPU with timing-error prevention and adaptive clocking in 28nm CMOS

A coprocessor for clock-mapping-based nearest Euclidean distance search with feature vector dimension adaptability

An efficiency-enhanced 2.4GHz stacked CMOS power amplifier with mode switching scheme for WLAN applications

A capacitive-coupling technique with phase noise and phase error reduction for multi-phase clock generation

A 127–140GHz injection-locked signal source with 3.5mW peak output power by zero-phase coupled oscillator network in 65nm CMOS

A 0.4-V, 500-MHz, ultra-low-power phase-locked loop for near-threshold voltage operation

A 75mW 50Gbps SerDes transmitter with automatic serializing time window search in 65nm CMOS technology

A blind ADC-based CDR with digital data interpolation and adaptive CTLE and DFE

Wireline clocking and equalization

Design technology co-optimization for 10 nm and beyond

Design for data-center, low-power and SoCs

Power management

Low power transceivers and oscillators

Amplifiers and filters

Wireline transceivers

Embedded tutorial: Test and manufacturability for silicon photonics and 3D integration

Bio-systems at Gigahertz

Sub-session: Data converter techniques

Testability and reliability enhancement techniques

Challenges for analog nanoscale technology

Analog techniques

Advanced simulation techniques

Energy-efficient bio-sensing systems

Modeling of advanced devices

Advanced memory topics

Linear current-controlled oscillator for analog to digital conversion

A fully integrated translational tracking filter with >40dB blocker attenuation and >68dB harmonic rejection in 40nm for Digital TV tuner applications

An area-efficient 12-bit 1.25MS/s radix-value self-estimated non-binary ADC with relaxed requirements on analog components

A 5mW 250MS/s 12-bit synthesized digital to analog converter

Inherently linear time symmetric pulse width modulation

A VCO-based ADC employing a multi-phase noise-shaping beat frequency quantizer for direct sampling of Sub-1mV input signals

A 65 nm CMOS tunable 0.1-to-1.6 GHz distributed transmission line N-path filter with +10 dBm blocker tolerance

A 0.8V 140nW low-noise energy harvesting CMOS APS imager with fully digital readout

A bidirectional neural interface SoC with an integrated spike recorder, microstimulator, and low-power processor for real-time stimulus artifact rejection

Mixed-signal stochastic computation demonstrated in an image sensor with integrated 2D edge detection and noise filtering

A 14pJ/pulse-TX, 0.18nJ/b-RX, 100Mbps, channelized, IR-UWB transceiver for centimeter-to-meter range biotelemetry

SRAM read performance degradation under asymmetric NBTI and PBTI stress: Characterization vehicle and statistical aging data

A methodology for yield-specific leakage estimation in memory

Anti-ESL/ESR variation robust constant-on-time control for DC-DC buck converter in 28nm CMOS technology

Impact of inductive integrated voltage regulator on the power attack vulnerability of encryption engines: A simulation study

True Random Number Generator circuits based on single- and multi-phase beat frequency detection

Energy-efficient Mixed-mode support vector machine processor with analog Gaussian kernel

Characterization of radiation-induced SRAM and logic soft errors from 0.33V to 1.0V in 65nm CMOS

A wideband RF receiver with >80 dB harmonic rejection ratio

85-to-127 GHz CMOS transmitter for rotational spectroscopy

A 135GHz SiGe transmitter with a dielectric rod antenna-in-package for high EIRP/channel arrays

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference

2011 IEEE Custom Integrated Circuits Conference (CICC)

IEEE Custom Integrated Circuits Conference 2010

2009 IEEE Custom Integrated Circuits Conference

2008 IEEE Custom Integrated Circuits Conference

2007 IEEE Custom Integrated Circuits Conference

IEEE Custom Integrated Circuits Conference 2006

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005.

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)

Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003.

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)

Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327)

Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143)

Proceedings of CICC 97 - Custom Integrated Circuits Conference

Proceedings of Custom Integrated Circuits Conference

Proceedings of the IEEE 1995 Custom Integrated Circuits Conference

Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94

Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93

1992 Proceedings of the IEEE Custom Integrated Circuits Conference

Proceedings of the IEEE 1991 Custom Integrated Circuits Conference

IEEE Proceedings of the Custom Integrated Circuits Conference

1989 Proceedings of the IEEE Custom Integrated Circuits Conference

Proceedings of the IEEE 1988 Custom Integrated Circuits Conference

AMD SOC power management: Improving performance/watt using run-time feedback

Content Provider	IEEE Xplore Digital Library
Author	Bircher, W.L. Naffziger, S.
Copyright Year	2014
Description	Author affiliation: Adv. Micro Devices, USA (Bircher, W.L.; Naffziger, S.)
Abstract	This paper presents an analysis of four runtime power management features implemented in AMD's recent 28nM APU. These features optimize SOC performance by shifting power and frequency resources in response to workload characteristics. The Global Efficient APM (GEAPM), Core-Bound Boost (CBB) and Memory-Bound Boost (MBB) features are shown to provide a performance improvement of up to 76%, 4.3% and 12.5% respectively. The Local Efficient APM (LEAPM) feature is shown to reduce average CPU power consumption by 34% while reducing performance by less than 1%.
Sponsorship	IEEE Electron Dev. Soc.
Starting Page	1
Ending Page	4
File Size	202788
Page Count	4
File Format	PDF
ISBN	9781479932863
DOI	10.1109/CICC.2014.6946043
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-09-15
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	System-on-chip Clocks Graphics processing units Power demand IP networks Temperature Monitoring workload analysis Power management SOC
Content Type	Text
Resource Type	Article

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