NDLI: SRAM read performance degradation under asymmetric NBTI and PBTI stress: Characterization vehicle and statistical aging data

Content Provider	IEEE Xplore Digital Library
Author	Xiaofei Wang Weichao Xu Kim, C.H.
Copyright Year	2014
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Univ. of Minnesota, Minneapolis, MN, USA (Xiaofei Wang; Weichao Xu; Kim, C.H.)
Abstract	Asymmetric BTI aging in circuit paths has shown to cause a time dependent shift in the signal's duty cycle, affecting the performance of circuits such as low power SRAMs whose operation rely on both the positive and negative edges of the clock signal. In this work, we propose the first known on-chip reliability monitor to accurately characterize the impact of asymmetric BTI on SRAM read speed. Statistical data collected from test chip built in a 32nm high-k metal-gate technology shows that (i) the average SRAM read frequency decreases with stress while its variation increases with stress and (ii) both μ and σ of read frequency shift follow a power law dependence on stress time. These observations point to the impact of SRAM peripheral circuit aging on read performance, and the utility of the proposed monitor for characterizing circuit level reliability concerns.
Sponsorship	IEEE Electron Dev. Soc.
Starting Page	1
Ending Page	4
File Size	480849
Page Count	4
File Format	PDF
ISBN	9781479932863
DOI	10.1109/CICC.2014.6946132
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-09-15
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Random access memory Stress Clocks Frequency measurement Aging Reliability Delays peripheral circuits SRAM read degradation BTI asymmetric aging
Content Type	Text
Resource Type	Article

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