NDLI: Design considerations for low-power analog front ends in full-duplex 10GBASE-T transceivers

Content Provider	IEEE Xplore Digital Library
Author	Westra, J.R. Mulder, J. Yi Ke Vecchi, D. Xiaodong Liu Arslan, E. Jiansong Wan Qiongna Zhang Wang, S. van der Goes, F. Bult, K.
Copyright Year	2014
Description	Author affiliation: Broadcom Netherlands B.V., Bunnik, Netherlands (Westra, J.R.; Mulder, J.; Yi Ke; Vecchi, D.; Xiaodong Liu; Arslan, E.; Jiansong Wan; Qiongna Zhang; Wang, S.; van der Goes, F.; Bult, K.)
Abstract	The speed of Ethernet over copper cables has steadily increased by a factor of 10,000 over the last four decades, from 1Mb/s in the earliest Ethernet implementations to 10Gb/s in recent systems. This paper describes the design considerations on all levels of the 10GBASE-T design hierarchy that form the basis for the implementation of highly power-efficient AFEs in full-duplex 10GBASE-T transceivers. It also shows how these considerations are implemented in a practical design. At frequencies up to 400MHz, the transceiver presented in this paper achieves >62dBc transmitter SFDR, >62dBc echo cancellation (EC) SFDR and >60dB receiver SFDR. Achieving a bit-error-rate (BER) better than $10^{-15},$ it dissipates less than 1.75W at full 10Gb/s traffic over a 100m cable, which is the lowest power for a 10GBASE-T AFE published to date.
Sponsorship	IEEE Electron Dev. Soc.
Starting Page	1
Ending Page	8
File Size	1280567
Page Count	8
File Format	PDF
ISBN	9781479932863
DOI	10.1109/CICC.2014.6945981
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-09-15
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Transceivers Receivers Transmitters Computer architecture Electronics packaging Impedance Hybrid power systems Ethernet networks Communication systems CMOS integrated circuits Digital communication
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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