NDLI: A 1.1V 2y-nm 4.35Gb/s/pin 8Gb LPDDR4 mobile device with bandwidth improvement techniques

Content Provider	IEEE Xplore Digital Library
Author	Keunsoo Song Sangkwon Lee Dongkyun Kim Youngbo Shim Sangil Park Bokrim Ko Duckhwa Hong Yongsuk Joo Wooyoung Lee Yongdeok Cho Wooyeol Shin Jaewoong Yun Hyengouk Lee Jeonghun Lee Eunryeong Lee Jaemo Yang Haekang Jung Namkyu Jang Joohwan Cho Hyeongon Kim
Copyright Year	2014
Description	Author affiliation: Jinkook Kim SK hynix, Icheon, South Korea (Keunsoo Song; Sangkwon Lee; Dongkyun Kim; Youngbo Shim; Sangil Park; Bokrim Ko; Duckhwa Hong; Yongsuk Joo; Wooyoung Lee; Yongdeok Cho; Wooyeol Shin; Jaewoong Yun; Hyengouk Lee; Jeonghun Lee; Eunryeong Lee; Jaemo Yang; Haekang Jung; Namkyu Jang; Joohwan Cho; Hyeongon Kim)
Abstract	The demands on higher bandwidth with reduced power consumption in mobile market are driving mobile DRAM to have advanced design techniques. Proposed LPDDR4 in this paper achieves over 30% improved power efficiency and over 4.3Gbps data rate with 1.1V supply voltage. These are challenging target comparing with that of LPDDR3. This works includes various techniques including multi-channel per die, various trainings, low swing interface, DQS and clock frequency dividing, internal reference voltage for data and command-address signals and so on. This chip was fabricated in a 3-metal 2y-nm DRAM CMOS process.
Sponsorship	IEEE Electron Dev. Soc.
Starting Page	1
Ending Page	4
File Size	784890
Page Count	4
File Format	PDF
ISBN	9781479932863
DOI	10.1109/CICC.2014.6946032
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-09-15
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Training Random access memory Timing Computer aided software engineering Frequency conversion Bandwidth dram interface DRAM LPDDR4 memory architecture training
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A 1.1 V 2y-nm 4.35 Gb/s/pin 8 Gb LPDDR4 Mobile Device With Bandwidth Improvement Techniques

A 4.35Gb/s/pin LPDDR4 I/O interface with multi-VOH level, equalization scheme, and duty-training circuit for mobile applications

Taking DRAM from 4 MBytes/s to 4 GBytes/s

25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation

A 5.6 ns random cycle 144 Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface

Performance analysis of multi-bank DRAM with increased clock frequency

A 6.4Gb/s/pin at sub-1V supply voltage TX-interleaving technique for mobile DRAM interface

An SDRAM interface for simplified "at-speed" testing of the SLDRAM internal array

A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques

A 1.1V 2y-nm 4.35Gb/s/pin 8Gb LPDDR4 mobile device with bandwidth improvement techniques

Similar Documents

A 1.1 V 2y-nm 4.35 Gb/s/pin 8 Gb LPDDR4 Mobile Device With Bandwidth Improvement Techniques

A 4.35Gb/s/pin LPDDR4 I/O interface with multi-VOH level, equalization scheme, and duty-training circuit for mobile applications

Taking DRAM from 4 MBytes/s to 4 GBytes/s

25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation

A 5.6 ns random cycle 144 Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface

Performance analysis of multi-bank DRAM with increased clock frequency

A 6.4Gb/s/pin at sub-1V supply voltage TX-interleaving technique for mobile DRAM interface

An SDRAM interface for simplified "at-speed" testing of the SLDRAM internal array

A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques

A 1.1V 2y-nm 4.35Gb/s/pin 8Gb LPDDR4 mobile device with bandwidth improvement techniques