NDLI: Implementation of pulsed-latch and pulsed-register circuits to minimize clocking power

Content Provider	IEEE Xplore Digital Library
Author	Seungwhun Paik Gi-Joon Nam Youngsoo Shin
Copyright Year	2011
Description	Author affiliation: Dept. of Electrical, Engineering, KAIST, Daejeon 305 - 701, Korea (Youngsoo Shin) \|\| IBM Austin Research, Laboratory, Austin, Texas (Gi-Joon Nam) \|\| Dept. of Electrical, Engineering, KAIST, Daejeon 305-701, Korea (Seungwhun Paik)
Abstract	A pulsed-latch can be modeled as a fast flip-flop. This allows conventional flip-flop designs to be migrated to pulsed-latch versions by simple replacement to reduce the clocking power. A key step in the migration process is to insert pulsers, which generate clock pulse to drive local latches; the number of pulsers as well as the wirelength of clock routing must be minimized to reduce the clocking power. We formulate a pulser insertion problem to find a set of latch groups where each group shares a pulser and its load constraint is satisfied; both an ILP formulation and a heuristic algorithm are presented to solve the problem. Experimental results of circuits implemented with 32-nm CMOS technology show that the clocking power of pulsed-latch designs obtained by our approach is 5.9% less than that of greedy approach; this is 44.7% less than that of flip-flop designs. We also consider the problem of pulsed-register where a pulser is integrated with multiple latches. A concept of logical distance is explored during our clustering algorithm to minimize the overhead of signal wirelength when converting flip-flops to pulsed-registers. Compared with flip-flop circuits, signal wirelength is increased by 6.3%, which is 1.4% smaller than without considering logical distance, while reducing the clocking power by 24%.
Starting Page	640
Ending Page	646
File Size	477755
Page Count	7
File Format	PDF
ISBN	9781457713996
ISSN	10923152
e-ISBN	9781457714009
e-ISBN	9781457713989
DOI	10.1109/ICCAD.2011.6105397
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-11-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Latches Clocks Capacitance Wires Merging Clustering algorithms Logic gates low clocking power Pulsed-latch pulsed-register
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Computer Science Applications Software

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