NDLI: A corner stitching compliant $B^{∗}-tree$ representation and its applications to analog placement

Content Provider	IEEE Xplore Digital Library
Author	Hui-Fang Tsao Pang-Yen Chou Shih-Lun Huang Yao-Wen Chang Lin, M.P.-H. Duan-Ping Chen Liu, D.
Copyright Year	2011
Description	Author affiliation: Lattice Semiconductor Corp., San Jose, CA, USA (Duan-Ping Chen) \|\| Department of Electrical Engineering, National Chung Cheng University, Chia-Yi, Taiwan (Lin, M.P.-H.) \|\| Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan (Hui-Fang Tsao; Pang-Yen Chou; Shih-Lun Huang; Yao-Wen Chang) \|\| Synopsys Inc., Mountain View, CA, USA (Liu, D.)
Abstract	Modern circuit placement, especially analog placement, often needs to consider various constraints, such as symmetry, proximity, preplaced, variant, fixed-boundary, minimum separation, boundary, and fixed-outline constraints, for better electrical effects and higher performance. To handle these diverse constraints, topo-logical floorplan representations are pervasively used because of their higher flexibility and smaller solution space. Due to their intrinsic limitation in deriving module adjacency information directly from the representations themselves, however, they might incur difficulties in handling related constraints. In this paper, we work on $B^{∗}-trees,$ which have been shown to be most effective and efficient for floor-plan/placement problems, and present a corner stitching compliant $B^{∗}-tree$ (CB-tree, for short) to remedy the significant deficiency in its module adjacency handling. A CB-tree is a $B^{∗}-tree$ integrated with modified corner stitching to offer much higher flexibility/efficiency, especially for adjacent module identification/packing. Compared with the previous works, CB-trees can achieve the lowest time complexity for module packing with the aforementioned constraints. Experimental results show that the CB-trees achieve the best solution quality and consume the least running time for industrial designs with various constraints. In particular, our work provides key insights into the handling of comprehensive placement constraints with a topological representation.
Starting Page	507
Ending Page	511
File Size	565679
Page Count	5
File Format	PDF
ISBN	9781457713996
ISSN	10923152
e-ISBN	9781457714009
e-ISBN	9781457713989
DOI	10.1109/ICCAD.2011.6105377
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-11-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Tiles Layout Complexity theory Shape Solids Performance evaluation Routing
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Computer Science Applications Software

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