NDLI: Application-aware deadlock-free oblivious routing based on extended turn-model

Content Provider	IEEE Xplore Digital Library
Author	Shafiee, A. Zolghadr, M. Arjomand, M. Sarbazi-azad, H.
Copyright Year	2011
Description	Author affiliation: CE Department, Sharif University of Technology, Tehran, Iran (Shafiee, A.; Zolghadr, M.; Arjomand, M.; Sarbazi-azad, H.)
Abstract	Programmable hardware is gaining popularity as it can keep pace with growing performance demand in tight power budget, design and test cost, and serious reliability concerns of future multiprocessor embedded systems. Compatible with this trend, Network-on-Chip, as a potential bottleneck of future multi-cores, should also support pro-grammability. Here, we address this issue in design and implementation of routing algorithm for two-dimensional mesh. To this end, we allocate paths based on input traffic pattern and in parallel with customizing routing restriction for deadlock freedom. To achieve this, we propose extended turn model (ETM), a novel parametric deadlock-free routing for 2D meshes that generalize prior turn-based routing methods (e.g., odd-even) with great degree of freedoms. This model facilitates design of Mixed-Integer Linear Programming (MILP) approach, which considers channel dependency turns as independent variables and decides for both path allocation and routing restriction. We solve this problem by genetic algorithm and evaluate it using simulation experiments. Results reveal that application-aware ETM-based path allocation outperforms prior turn-based approaches under synthetic and real traffic loads.
Starting Page	213
Ending Page	218
File Size	1065126
Page Count	6
File Format	PDF
ISBN	9781457713996
ISSN	10923152
e-ISBN	9781457714009
e-ISBN	9781457713989
DOI	10.1109/ICCAD.2011.6105328
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-11-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Routing System recovery Genetic algorithms Jitter Resource management Throughput Clocks
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Computer Science Applications Software

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Application-aware deadlock-free oblivious routing based on extended turn-model

Application-aware deadlock-free oblivious routing.

An abacus turn model for time/space-efficient reconfigurable routing

A provably good algorithm for high performance bus routing

Turn-based Deadlock Detection for Wormhole Routed Networks

An Effective Design of Deadlock-Free Routing Algorithms Based on 2D Turn Model for Irregular Networks

Application-aware deadlock-free oblivious routing

Designing Application-Specific Networks on Chips with Floorplan Information

Designing application-specific networks on chips with floorplan information

Application-aware deadlock-free oblivious routing based on extended turn-model

Similar Documents

Application-aware deadlock-free oblivious routing based on extended turn-model

Application-aware deadlock-free oblivious routing.

An abacus turn model for time/space-efficient reconfigurable routing

A provably good algorithm for high performance bus routing

Turn-based Deadlock Detection for Wormhole Routed Networks

An Effective Design of Deadlock-Free Routing Algorithms Based on 2D Turn Model for Irregular Networks

Application-aware deadlock-free oblivious routing

Designing Application-Specific Networks on Chips with Floorplan Information

Designing application-specific networks on chips with floorplan information

Application-aware deadlock-free oblivious routing based on extended turn-model