NDLI: LatchPlanner: Latch placement algorithm for datapath-oriented high-performance VLSI designs

Content Provider	IEEE Xplore Digital Library
Author	Minsik Cho Hua Xiang Haoxing Ren Ziegler, M.M. Puri, R.
Copyright Year	2013
Description	Author affiliation: IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA (Minsik Cho; Hua Xiang; Haoxing Ren; Ziegler, M.M.; Puri, R.)
Abstract	In this paper, we present a novel algorithm for latch placement, LatchPlanner which enables a placement engine to deliver high quality placement for datapath-oriented design. Datapath-oriented VLSI designs are in general hand-crafted by human at high cost, as understanding and capturing datapath structure is critical for the performance. The conventional placement algorithms by itself cannot exploit the underlying datapath due to lack of logic structure recognition and inaccurate/approximated wirelength estimation. LatchPlanner addresses such drawbacks by placing and fixing latches in the datapath context, a key element in datapath structure. By taking placed/fixed latches as constraints, a placer can find a more datapath-friendly placement effectively, which results in higher-quality hardware. LatchPlanner begins latch clustering/sizing/ordering to prepare the following steps, a) global latch placement based on linear programming to place latch clusters, and b) local latch placement based on network flow optimization to place latches within each cluster. Experimental results on eighteen industrial benchmarks show that LatchPlanner improves total wirelength by 32%, total negative slack by 25%, and area by 3% without CPU overhead over a commercial placement engine, and delivers near semi-custom-quality solutions.
Sponsorship	IEEE Counc. Electron. Design Autom.
Starting Page	342
Ending Page	348
File Size	927476
Page Count	7
File Format	PDF
ISBN	9781479910717
ISSN	10923152
DOI	10.1109/ICCAD.2013.6691141
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-11-18
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Latches Pins Optimization Very large scale integration Clustering algorithms Algorithm design and analysis Logic gates
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Computer Science Applications Software

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