NDLI: Massively parallel programming models used as hardware description languages: The OpenCL case

Content Provider	IEEE Xplore Digital Library
Author	Owaida, M. Bellas, N. Antonopoulos, C.D. Daloukas, K. Antoniadis, C.
Copyright Year	2011
Description	Author affiliation: Department of Computer and Communication Engineering, University of Thessaly, Volos, Greece (Owaida, M.; Bellas, N.; Antonopoulos, C.D.; Daloukas, K.; Antoniadis, C.)
Abstract	The problem of automatically generating hardware modules from high level application representations has been at the forefront of EDA research during the last few years. In this paper, we introduce a methodology to automatically synthesize hardware accelerators from OpenCL applications. OpenCL is a recent industry supported standard for writing programs that execute on multicore platforms and accelerators such as GPUs. Our methodology maps OpenCL kernels into hardware accelerators, based on architectural templates that explicitly decouple computation from memory communication whenever this is possible. The templates can be tuned to provide a wide repertoire of accelerators that meet user performance requirements and FPGA device characteristics. Furthermore, a set of high- and low-level compiler optimizations is applied to generate optimized accelerators. Our experimental evaluation shows that the generated accelerators are tuned efficiently to match the applications memory access pattern and computational complexity, and to achieve user performance requirements. An important objective of our tool is to expand the FPGA development user base to software engineers, thereby expanding the scope of FPGAs beyond the realm of hardware design.
Starting Page	326
Ending Page	333
File Size	921062
Page Count	8
File Format	PDF
ISBN	9781457713996
ISSN	10923152
e-ISBN	9781457714009
e-ISBN	9781457713989
DOI	10.1109/ICCAD.2011.6105349
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-11-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Kernel Hardware Field programmable gate arrays Synchronization Computational modeling Pipelines Optimization Embedded Systems OpenCL FPGA Electronic Design Automation Reconfigurable Computing
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Computer Science Applications Software

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