NDLI: Test-data volume and scan-power reduction with low ATE interface for multi-core SoCs

Content Provider	IEEE Xplore Digital Library
Author	Tenentes, V. Kavousianos, X.
Copyright Year	2011
Description	Author affiliation: Dept. of Computer Science, University of Ioannina (Tenentes, V.; Kavousianos, X.)
Abstract	Symbol-based and linear-based test-data compression techniques have complementary properties which are very attractive for testing multi-core SoCs. However, only linear-based techniques have been adopted by industry as the symbol-based techniques have not yet revealed their real potential for testing large circuits. We present a novel compression method and a low-cost decompression architecture that combine the advantages of both symbol-based and linear-based techniques under a unified solution for multi-core SoCs. The proposed method offers higher compression than any other method presented so far, very low shift switching activity and very short test sequence length at the same time. Moreover, contrary to existing techniques, it offers a complete solution for testing multi-core SoCs as it is suitable for cores of both known and unknown structure (IP cores) that usually co-exist in modern SoCs. Finally, it supports very low pin-count interface as it needs only one tester channel to download fast the compressed test data on-chip.
Starting Page	747
Ending Page	754
File Size	786744
Page Count	8
File Format	PDF
ISBN	9781457713996
ISSN	10923152
e-ISBN	9781457714009
e-ISBN	9781457713989
DOI	10.1109/ICCAD.2011.6105413
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-11-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Vectors Encoding System-on-a-chip Merging Testing Compaction Registers
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Computer Science Applications Software

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