NDLI: High-level synthesis with distributed controller for fast timing closure

Content Provider	IEEE Xplore Digital Library
Author	Seokhyun Lee Kiyoung Choi
Copyright Year	2011
Description	Author affiliation: Electrical Engineering and Computer Science, Seoul National University, Seoul, Korea (Seokhyun Lee; Kiyoung Choi)
Abstract	Centralized controllers commonly used in high-level synthesis often cause long wires and high load capacitance and that is why critical paths typically occur on paths from controllers to data registers. However, conventional high level synthesis has focused on the delay of datapaths making it difficult to solve the timing closure problem during physical synthesis. This paper presents a hardware architecture with a distributed controller, which makes the timing closure problem much easier. It also presents a novel high-level synthesis flow for synthesizing such hardware through datapath partitioning and controller optimization. According to our experimental results, the proposed approach reduces the controller and interconnect delay by 20.3–27.4% and the entire critical path delay by 6.6∼10.3% with 0.2∼13.3% area overhead. Even without area overhead, it reduces the critical path delay by 5.8∼10%.
Starting Page	193
Ending Page	199
File Size	1135935
Page Count	7
File Format	PDF
ISBN	9781457713996
ISSN	10923152
e-ISBN	9781457714009
e-ISBN	9781457713989
DOI	10.1109/ICCAD.2011.6105325
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-11-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Registers Delay Capacitance Partitioning algorithms Optimization Wires Integrated circuit interconnections timing closure high level synthesis distributed controller controller optimization
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Computer Science Applications Software

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