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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Yiyi Ma Kim-Yong Goh Xueren Zhang Yonggang Jin |
| Copyright Year | 2013 |
| Description | Author affiliation: STMicroelectron., Singapore, Singapore (Yiyi Ma; Kim-Yong Goh; Xueren Zhang; Yonggang Jin) |
| Abstract | With great feasibility and flexibility for growing I/Os, multi-chips and system integration, the emerging fan-out embedded Wafer Level BGA (eWLB) technology is regarded as a much more favorable packaging solution compared with its traditional counterparts, i.e. fan-in WLP or BGA technology. The relentless trend of ever increasing integrated circuit chip functionality and decreasing chip dimensions for miniaturization of products have led to less chip real estate and intense heat dissipation. While eWLB technology has well addressed the routing problems associated with the former, its intrinsic ineffectiveness of reducing the spreading thermal resistance of the shrunk die has limited its application to low power devices. As a result, Quad Flat No-Lead (QFN) is often a packaging technology of choice for those applications as QFN is a lead frame based package which offers thermal and electrical enhancement with its exposed die pad on the bottom of the package surface. The exposed die pad not only provides an efficient heat path to the PCB, but also enables stable grounding with electrical connection through a conductive die attach material. To bridge the gap between the eWLB and QFN concept so that both of their advantages can be retained, STMicroelectronics has recently come up with a QFN-like eWLB package known as embedded wafer level LGA (eWLL) with low profile, high pin count and excellent thermal and electrical performance. This paper initially investigated the solder joint reliability of the eWLL packages under board level Accelerated Thermal Cycling (ATC) test through Finite Element Analysis (FEA). Experiments were then carried out to assess the accuracy of the FEA model. It was found that the predictions made by the FEA simulation correlated very well with the actual test results. The validated FEA model was then extended to study the effect of a wide range of design variables on the board level reliability of the eWLL packages. The results of the numerical analysis are compared and discussed in details. |
| Sponsorship | IEEE Singapore Sect. |
| Starting Page | 606 |
| Ending Page | 611 |
| File Size | 1567480 |
| Page Count | 6 |
| File Format | |
| e-ISBN | 9781479928347 |
| DOI | 10.1109/EPTC.2013.6745792 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-12-11 |
| Publisher Place | Singapore |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Soldering Electronic packaging thermal management Reliability Packaging Heating Finite element analysis |
| Content Type | Text |
| Resource Type | Article |
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