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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Lenihan, T.G. Matthew, L. Vardaman, E.J. |
| Copyright Year | 2013 |
| Description | Author affiliation: TechSearch Int., Inc., Austin, TX, USA (Lenihan, T.G.; Matthew, L.; Vardaman, E.J.) |
| Abstract | Silicon interposers are a technology with a history of multiple incarnations over more than 20 years. Today, interposers with TSVs are considered an alternative to 3D IC structures where die are stacked on top of each other using TSVs. Applications for interposers with TSVs include ASICs for networking applications and FPGAs. Xilinx's Virtex-7 2000T FPGA was one of the first new products using a silicon interposer with TSVs for a partitioned IC design. Co-design with new packaging technology has resulted in a new FPGA that allows reduced system cost and increased performance with lower power. By not having to drive off-chip I/Os across PCB traces to adjacent FPGAs, high-performance applications that have previously used multiple FPGAs can be replaced with a single package solution that provides high-bandwidth, low-latency, power-efficient interconnect between the FPGA die. The key to the performance gains is the partitioning of an FPGA die into four “slices” that are mounted on a silicon interposer. Is this a unique application or are there other potential applications for interposers in applications with GPUs or ASICs? Today's interposers are passive structures, but there are potential for the use of integrated passives in the interposer. How do these applications differ from the technology introduced in previous generations? This presentation highlights the new drivers for the introduction of silicon interposers. The presentation also examines the latest developments in the infrastructure to support the development of this technology, including suppliers. The article also highlights the differences between adoption of today's interposers and the thin-film on silicon (MCM-D) of the past. |
| Sponsorship | IEEE Singapore Sect. |
| Starting Page | 53 |
| Ending Page | 55 |
| File Size | 243577 |
| Page Count | 3 |
| File Format | |
| e-ISBN | 9781479928347 |
| DOI | 10.1109/EPTC.2013.6745683 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-12-11 |
| Publisher Place | Singapore |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Silicon Field programmable gate arrays Substrates Packaging Three-dimensional displays Companies Laminates |
| Content Type | Text |
| Resource Type | Article |
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