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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Chong Chin Hui Wang Ai Chie |
| Copyright Year | 2013 |
| Description | Author affiliation: Micron Semicond. Asia Pte. Ltd., Singapore, Singapore (Chong Chin Hui; Wang Ai Chie) |
| Abstract | Due to intense competition in the consumer electronics landscape, especially in the mobile communication products sector, new memory products (both DRAM and NAND Flash) must meet higher speed requirements, be packaged in smaller form factors, and achieve higher densities. Therefore, the most common package types-board on chip (BOC) for DRAM and chip on board (COB) for NAND Flash-must be analyzed to determine whether they can meet current and future packaging challenges. The components of COB and BOC substrates that are being studied are traces, bond fingers, the number of metal layers, and vias. Based on the trends of these substrate components, future substrates will be required to have at least two metal layers (BOC in particular), utilize narrower bond finger pitches, be thinner than 0.13mm and have vias with via land/drill hole sizes of less than 220μm/100μm. Further work must be performed to determine the minimum required trace width value based on the existing warpage specifications as well as the minimum required bond finger pitch as a function of die length. |
| Sponsorship | IEEE Singapore Sect. |
| Starting Page | 731 |
| Ending Page | 735 |
| File Size | 536109 |
| Page Count | 5 |
| File Format | |
| e-ISBN | 9781479928347 |
| DOI | 10.1109/EPTC.2013.6745817 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-12-11 |
| Publisher Place | Singapore |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Substrates Metals Random access memory Wires Flash memories Thumb |
| Content Type | Text |
| Resource Type | Article |
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