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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Seung Wook Yoon Andy, L.K.J. Ganesh, V.P. Kripesh, V. |
| Copyright Year | 2004 |
| Description | Author affiliation: Inst. of Microelectron., Singapore (Seung Wook Yoon) |
| Abstract | Systems in package (SiP) allow a greater density of silicon devices (IC) to be mounted directly onto a substrate within a single component package. Further miniaturization in microelectronics system requires 3D integration of active, passive or module components. In order to maintain signal integrity, approaches featuring much shorter, impedance-matched, and less-interconnect-level between chips and passive components are desired, leading to the functional integration. In order to realise miniaturized functional modules, embedding actives and passives is potential baseline. Wafer level integration enables low cost and mass manufacturability of micro modules. In this work, embedding a silicon chip into a wafer level cavity layer was attempted and presented. The polymer module process is investigated using a thick polymer photoresist to create a multi-layered 3D structure with microchip integration. SU-8 was used as the polymer thick layer to give the carrier structure for the embedding of silicon chip or device. SU-8 with its high aspect ratio capabilities and good photosensitivity, enabled to create a good base structure for embedding silicon chip. Experiments were carried out in the following stages to determine the feasibility of the process. Silicon substrate was coated with a thick SU-8 layer of 100mum and developed to form the base substrate. On this base silicon test chip were die-attached and a passivation dielectric layer was deposited and developed over the passivation layer UBM and metal layer were deposited for interconnection and bumping. The prototype samples with 3.5mmtimes3.5mm dies having 70mum thickness were successfully thinned. The embedded module was then coated with a dielectric and interconnection processes were followed. The test vehicles showed electrical connectivity and the embedded module technology can be further used in the field of advanced microelectronics or microsystem packaging. The solution to 3D wafer level integration whilst having smaller systems and components can also be achieved using this embedded module technology |
| Starting Page | 600 |
| Ending Page | 604 |
| File Size | 423988 |
| Page Count | 5 |
| File Format | |
| ISBN | 0780388216 |
| DOI | 10.1109/EPTC.2004.1396678 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2004-12-08 |
| Publisher Place | Singapore |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Polymers Dielectric substrates Integrated circuit packaging Microelectronics Testing Passivation Silicon devices Impedance Costs Manufacturing |
| Content Type | Text |
| Resource Type | Article |
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