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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Wei-Chung Lo Li-Cheng Shen Shu-Ming Chang Yu-Chih Chen Hsu-Tien Hu Jyh-Rong Lin Kuo-Chuan Chen Yu-Jiau Hwang |
| Copyright Year | 2002 |
| Description | Author affiliation: Adv. Process Technol. Dept., APC/ERSO/lTRI, Hsinchu, Taiwan (Wei-Chung Lo; Li-Cheng Shen; Shu-Ming Chang; Yu-Chih Chen; Hsu-Tien Hu; Jyh-Rong Lin; Kuo-Chuan Chen; Yu-Jiau Hwang) |
| Abstract | In this paper, one of the wafer level chip scale packaging (WL-CSP) patents issued by ERSO/ITRI, the double elastomer wafer level package, is implemented on the test vehicle of Rambus DRAM to demonstrate the applicability and reliability of WL-CSP for high performance devices. In this design, both thermal and electrical performance enhancements are considered. To demonstrate the reliability of the enhanced WL-CSP, both the component- and board-level criteria are studied, which includes the evaluation of UBM (under bump metallurgy) by adopting low cost electroless and electroplating Ni/Au processes. Results show that the developed thermally and electrically enhanced WL-CSP can pass the reliability tests of pre-con, TC (temperature cycling), PCT (pressure cooker test), and HST (humidity storage test) at component-level and PCT at board-level. Although the board-level TC is on-going, which targets 1000 cycles, early studies of typical FMA are presented here. Moreover, preliminary studies of improving the board-level TC reliability are also included in the paper. |
| Starting Page | 218 |
| Ending Page | 222 |
| File Size | 827541 |
| Page Count | 5 |
| File Format | |
| ISBN | 0780374355 |
| DOI | 10.1109/EPTC.2002.1185671 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2002-12-10 |
| Publisher Place | Singapore |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Wafer scale integration Testing Chip scale packaging Vehicles Costs Electronic packaging thermal management Buffer layers Temperature Process design Random access memory |
| Content Type | Text |
| Resource Type | Article |
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