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Content Provider | IEEE Xplore Digital Library |
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Author | Umemoto, M. Tanida, K. Tomita, Y. Takahashi, T. Takahashi, K. |
Copyright Year | 2002 |
Description | Author affiliation: Assoc. of Super-Adv. Electron. Technol. (ASET), Tsukuba Res. Center, Ibaraki, Japan (Umemoto, M.; Tanida, K.; Tomita, Y.; Takahashi, T.; Takahashi, K.) |
Abstract | The chip-stacking technologies with the thin devices in hyperfine pitch realize both of the strong demands for the high-speed signal transmission and the high-density packaging. The results of the experiments on the non-metallurgical bonding and encapsulation with nonconductive particle paste (NCP) are introduced. It realizes void-free encapsulation of under 10-/spl mu/m-thick gap, small warpage of 50-/spl mu/m-thick chip, and ohmic contact of all of 1844 bumps in 20-/spl mu/m-pitch. Additionally, it is found the flatness of chip backside is achieved sufficient level for the thin chip stacking process with hyper fine pitch interconnection. |
Starting Page | 285 |
Ending Page | 288 |
File Size | 803380 |
Page Count | 4 |
File Format | |
ISBN | 0780374355 |
DOI | 10.1109/EPTC.2002.1185684 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2002-12-10 |
Publisher Place | Singapore |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Bonding Large scale integration Encapsulation Gold Stacking Electronics packaging Ohmic contacts Wiring Copper Electrodes |
Content Type | Text |
Resource Type | Article |
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