NDLI: RFICs packages electrical performance comparison of both ULTRA-CSP and Standard TSOP

Content Provider	IEEE Xplore Digital Library
Author	Hsu, T. Chiang, K. Yu-Po Wang
Copyright Year	2002
Description	Author affiliation: Siliconware Precision Industries Co. Ltd., Taichung, Taiwan (Hsu, T.; Chiang, K.; Yu-Po Wang)
Abstract	The requirement for low cost, small size and high density for high-speed system drives the design of packages to smaller package size. ULTRA CSP is an advanced technology to meet the above targets. ULTRA CSP is a wafer level package developed by FCT. Under high frequency operation, the parasitics associated with the package will significantly degrade the package performance. An unsuitable package may cause resonance, coupling, impedance mismatch and frequency dependent loss. So, providing accurate package parasitics is critical to the success of the system design. In this paper, the electrical model of ULTRA CSP has been established based on the S-parameter simulation. When compared with the TSOP package, ULTRA-CSP shows smaller parasitics in the equivalent model. This paper also compares the performance of the ULTRA-CSP and Standard TSOP from the view point of propagation delay, crosstalk noise, insertion loss, return loss and maximum allowable working frequency. Based on the analysis result, is provided the package layout guideline for designer reference.
Starting Page	25
Ending Page	31
File Size	1340384
Page Count	7
File Format	PDF
ISBN	0780374355
DOI	10.1109/EPTC.2002.1185591
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-12-10
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Radiofrequency integrated circuits Wafer scale integration Chip scale packaging Frequency Insertion loss Propagation losses Costs Degradation Resonance Impedance
Content Type	Text
Resource Type	Article

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