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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Yi-Hsuan Hsiao Hang-Ting Lue Wei-Chen Chen Chih-Ping Chen Kuo-Ping Chang Yen-Hao Shih Bing-Yue Tsui Chih-Yuan Lu |
| Copyright Year | 2012 |
| Description | Author affiliation: Macronix International Co., Ltd., 16 Li-Hsin Road, Hsinchu Science Park, Hsinchu, Taiwan (Yi-Hsuan Hsiao; Hang-Ting Lue; Wei-Chen Chen; Chih-Ping Chen; Kuo-Ping Chang; Yen-Hao Shih; Chih-Yuan Lu) || National Chiao-Tung University, 16 Li-Hsin Road, Hsinchu Science Park, Hsinchu, Taiwan (Bing-Yue Tsui) |
| Abstract | The variability of the poly silicon thin film transistor (TFT) in 3D NAND Flash is a major concern. In this work, we have fabricated and characterized a 37.5nm half pitch 3D Vertical Gate (VG) NAND Flash, and successfully modeled the random grain boundary effect using TCAD simulation. In our model, the grain boundary creates interface states, resulting in large local band bending and a surface potential barrier. The gate-induced grain barrier lowering (GIGBL) and drain-induced grain barrier lowering (DIGBL) effects are the major physical mechanisms that affect the subthreshold behavior. By means of modeling, the impact of bit line (BL) and word line (WL) critical dimensions (CD) of the double-gate TFT device is studied extensively, where we find that narrower BL and larger WL CD's are the most critical parameters that provide tight Vt distribution and good memory window. For the first time, we have discovered an asymmetry of reverse read (RR) and forward read (FR) of the TFT device. The physical mechanism can be well explained by the DIGBL. With accurate modeling, the asymmetry of RR and FR can be used to determine the GB trap lateral location and interface trap density. |
| File Size | 1097479 |
| File Format | |
| ISBN | 9781467348720 |
| ISSN | 2156017X |
| e-ISBN | 9781467348713 |
| e-ISBN | 9781467348706 |
| DOI | 10.1109/IEDM.2012.6479111 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2012-12-10 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Grain boundaries Thin film transistors Logic gates Arrays Silicon Flash memory Electric potential |
| Content Type | Text |
| Resource Type | Article |
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