NDLI: Designing closer to the edge [deep submicron processes]

Content Provider	IEEE Xplore Digital Library
Author	Nassif, S.R.
Copyright Year	2000
Description	Author affiliation: IBM Austin Res. Lab., TX, USA (Nassif, S.R.)
Abstract	Summary form only given. Modern deep submicron CMOS processes cost /spl Theta/ or more to develop, qualify and deploy. Yet the incremental impact of each technology generation has been steadily decreasing due to a variety of phenomena such as increasing wire delay, power dissipation and reliability limits, and increasing process tolerances. We need to make better use of existing and future manufacturing processes in order to recoup our investment. It is often possible to obtain more performance out of an existing technology by better understanding of the process tolerances and trading off functional yield vs. performance. Given the above, it is clear that we need to understand and model design tolerances arising from processing variations. Until recently, it was sufficient to model such process-induced variations as intra-die shifts in device performance. However, in the deep submicron regime, within-die wire and device variations are comparable to die-to-die variations. This results in the need for new characterization, modeling and analysis techniques to handle these variations. In this work we expand on the ideas above, review the important trends in design uncertainty which directly drives design tolerance and hence performance. We review a number of research and applied approaches to design for manufacturability. The need to track process tolerances as a technology matures is stressed. This tracking is important since it acts as an information conduit between design and fabrication groups and enables designers to adapt the design to lower tolerances where possible.
Starting Page	636
Ending Page	637
File Size	40140
Page Count	2
File Format	PDF
ISBN	0769505376
DOI	10.1109/DATE.2000.840852
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-03-30
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Wire CMOS process Costs CMOS technology Power generation Delay Power dissipation Manufacturing processes Investments Uncertainty
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Designing closer to the edge (2000).

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Designing closer to the edge [deep submicron processes]

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