NDLI: Power and delay reduction via simultaneous logic and placement optimization in FPGAs

Content Provider	IEEE Xplore Digital Library
Author	Kumthekar, B. Somenzi, F.
Copyright Year	2000
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA (Kumthekar, B.)
Abstract	Traditional FPGA design flows have treated logic synthesis and physical design as separate steps. With the recent advances in technology the lack of information on the physical implementation during logic synthesis has caused mismatches between the final circuit characteristics (delay, power and area) and those predicted by logic synthesis. In this paper, we present a technique that tightly links the logic and physical domains-we combine logic and placement optimization in a single step. The combined algorithm is based on simulation annealing and hence, very amenable to new optimization goals or constraints. Two types of moves, directed towards global reduction in the cost function (linear congestion), are accepted by the simulated annealing algorithm: (1) logic optimization steps consisting of removing or replacing redundant wires in a circuit using functional flexibilities derived from SPFDs and (2) the placement optimization steps consisting of swapping a pair of blocks in the FPGA. Feedback from placement is very valuable in making an informed choice of a target wire during logic optimization moves. Experimental results demonstrate the efficacy of our approach over the placement independent approach.
Starting Page	202
Ending Page	207
File Size	64571
Page Count	6
File Format	PDF
ISBN	0769505376
DOI	10.1109/DATE.2000.840039
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-03-30
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Delay Circuit synthesis Logic circuits Field programmable gate arrays Circuit simulation Simulated annealing Logic design Constraint optimization Cost function Wires
Content Type	Text
Resource Type	Article

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