NDLI: An evaluation of CMOS adders in deep submicron processes

Content Provider	IEEE Xplore Digital Library
Author	Gera, R.J. Hoe, D.H.K.
Copyright Year	2012
Description	Author affiliation: Department of Electrical Engineering, The University of Texas at Tyler (Gera, R.J.; Hoe, D.H.K.)
Abstract	An evaluation of various adders that are representative of different CMOS logic design styles is carried out for nanoscale CMOS technologies using a Predictive Technology Model from [1]. The adders under consideration are the static CMOS mirror adder, the Complementary Pass-transistor Logic (CPL) adder, the Transmission Gate Adder (TGA), and the Hybrid-CMOS adder (HCMOS). The adders are evaluated in terms of delay, power dissipation, voltage scalability, and area. Because scaling of the voltage supply to less than 1 V results in gate overdrive factors of less than 0.5 V, it is found that adders that maintain the optimum signal paths for both high and low signals (the mirror and TGA adders) had the best performance metrics when scaled to the deep submicron regime. The adders that rely upon PMOS feedback for signal restoration (the CPL and HCMOS designs) experienced significant degradation in performance at low power supply voltages.
Starting Page	126
Ending Page	129
File Size	580589
Page Count	4
File Format	PDF
ISBN	9781457714924
ISSN	00942898
e-ISBN	9781457714931
DOI	10.1109/SSST.2012.6195123
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-03-11
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Adders CMOS integrated circuits Logic gates Delay Capacitance CMOS technology Power dissipation
Content Type	Text
Resource Type	Article

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