NDLI: A VHDL error simulator for functional test generation

Content Provider	IEEE Xplore Digital Library
Author	Fin, A. Fummi, F.
Copyright Year	2000
Description	Author affiliation: DST Inf., Univ. di Verona, Italy (Fin, A.)
Abstract	This paper describes an efficient error simulator able to analyze functional VHDL descriptions. The proposed simulation environment can be based on commercial VHDL simulators. All components of the simulation environment are automatically built starting from the VHDL specification of the description under test. The effectiveness of the simulator has been measured by using a random functional test generator. Functional test patterns produce, on some benchmarks, a higher gate-level fault coverage than the fault coverage achieved by a very efficient gate-level test pattern generator. Moreover, functional test generation requires a fraction of the time necessary to generate test at the gate level. This is due to the possibility of effectively exploring the test patterns space since error simulation is directly performed at the VHDL level.
Starting Page	390
Ending Page	395
File Size	56091
Page Count	6
File Format	PDF
ISBN	0769505376
DOI	10.1109/DATE.2000.840301
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-03-30
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware design languages Computational modeling Production Random number generation Read only memory Automatic testing Benchmark testing Formal verification Performance evaluation Microprocessors
Content Type	Text
Resource Type	Article

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