NDLI: How to solve the current memory access and data transfer bottlenecks: at the processor architecture or at the compiler level?

Content Provider	IEEE Xplore Digital Library
Author	Catthoor, F. Dutt, N.D. Kozyrakis, C.E.
Copyright Year	2000
Description	Author affiliation: IMEC, Leuven, Belgium (Catthoor, F.)
Abstract	Current processor architectures, both in the programmable and custom case, become more and more dominated by the data access bottlenecks in the cache, system bus and main memory subsystems. In order to provide sufficiently high data throughput in the emerging era of highly parallel processors where many arithmetic resources can work concurrently, novel solutions for the memory access and data transfer will have to be introduced. The crucial question we want to address is where one can expect these novel solutions to reside: will they be mainly innovative processor architecture ideas, or novel approaches in the application compiler/synthesis technology, or a mix.
Starting Page	426
Ending Page	433
File Size	58543
Page Count	8
File Format	PDF
ISBN	0769505376
DOI	10.1109/DATE.2000.840306
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-03-30
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware Parallel processing Multithreading Microprocessors Runtime Throughput Arithmetic Electronic switching systems Microarchitecture Memory management
Content Type	Text
Resource Type	Article

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How to solve the current memory access and data transfer bottlenecks: at the processor architecture or at the compiler level?